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[23.128.96.18]) by mx.google.com with ESMTP id a42si15419724edf.469.2021.02.14.23.00.52; Sun, 14 Feb 2021 23:01:31 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@suse.com header.s=susede1 header.b=IQ0cjTrz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=suse.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229652AbhBOG4E (ORCPT + 99 others); Mon, 15 Feb 2021 01:56:04 -0500 Received: from mx2.suse.de ([195.135.220.15]:51806 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229578AbhBOG4C (ORCPT ); Mon, 15 Feb 2021 01:56:02 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1613372115; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=Gb2YctauaZwx1wpb7VFmE/CdTXsDy0TKF2f3m6ky/to=; b=IQ0cjTrz20AhAVvJ2K+wanLj3F/5JLuQJvUBuMSW9EdUMgSwHK8yJ8yeibvVEmDOHsSlhp jc43rB2SAM0oPnVSOGncHvIp6rG1B38sZRwuKpspDqiOKfUe82ragNpfDL/VNLXybFn3Yh BjmwQBUiqRWEbOewn4ToXQxrn2lPL5s= Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 998F8ADDB; Mon, 15 Feb 2021 06:55:15 +0000 (UTC) To: Julien Grall , xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org Cc: Boris Ostrovsky , Stefano Stabellini References: <20210211101616.13788-1-jgross@suse.com> <20210211101616.13788-4-jgross@suse.com> From: =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= Subject: Re: [PATCH v2 3/8] xen/events: avoid handling the same event on two cpus at the same time Message-ID: Date: Mon, 15 Feb 2021 07:55:14 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="7zfISEbWiXTW2yLiOjoHHWptpgt3WYDwu" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --7zfISEbWiXTW2yLiOjoHHWptpgt3WYDwu Content-Type: multipart/mixed; boundary="PN3jkXVSs90bn2otpr7vqVYheMbLKyUDx"; protected-headers="v1" From: =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= To: Julien Grall , xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org Cc: Boris Ostrovsky , Stefano Stabellini Message-ID: Subject: Re: [PATCH v2 3/8] xen/events: avoid handling the same event on two cpus at the same time References: <20210211101616.13788-1-jgross@suse.com> <20210211101616.13788-4-jgross@suse.com> In-Reply-To: --PN3jkXVSs90bn2otpr7vqVYheMbLKyUDx Content-Type: multipart/mixed; boundary="------------E8383365BF43AE4646CD0A35" Content-Language: en-US This is a multi-part message in MIME format. --------------E8383365BF43AE4646CD0A35 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable On 14.02.21 22:34, Julien Grall wrote: > Hi Juergen, >=20 > On 11/02/2021 10:16, Juergen Gross wrote: >> When changing the cpu affinity of an event it can happen today that >> (with some unlucky timing) the same event will be handled on the old >> and the new cpu at the same time. >> >> Avoid that by adding an "event active" flag to the per-event data and >> call the handler only if this flag isn't set. >> >> Reported-by: Julien Grall >> Signed-off-by: Juergen Gross >> --- >> V2: >> - new patch >> --- >> =C2=A0 drivers/xen/events/events_base.c | 19 +++++++++++++++---- >> =C2=A0 1 file changed, 15 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/xen/events/events_base.c=20 >> b/drivers/xen/events/events_base.c >> index e157e7506830..f7e22330dcef 100644 >> --- a/drivers/xen/events/events_base.c >> +++ b/drivers/xen/events/events_base.c >> @@ -102,6 +102,7 @@ struct irq_info { >> =C2=A0 #define EVT_MASK_REASON_EXPLICIT=C2=A0=C2=A0=C2=A0 0x01 >> =C2=A0 #define EVT_MASK_REASON_TEMPORARY=C2=A0=C2=A0=C2=A0 0x02 >> =C2=A0 #define EVT_MASK_REASON_EOI_PENDING=C2=A0=C2=A0=C2=A0 0x04 >> +=C2=A0=C2=A0=C2=A0 u8 is_active;=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 /* Is event just being handled? */ >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 unsigned irq; >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 evtchn_port_t evtchn;=C2=A0=C2=A0 /* ev= ent channel */ >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 unsigned short cpu;=C2=A0=C2=A0=C2=A0=C2= =A0 /* cpu bound */ >> @@ -622,6 +623,7 @@ static void xen_irq_lateeoi_locked(struct irq_info= =20 >> *info, bool spurious) >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 info->eoi_time =3D 0; >> +=C2=A0=C2=A0=C2=A0 smp_store_release(&info->is_active, 0); >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 do_unmask(info, EVT_MASK_REASON_EOI_PEN= DING); >> =C2=A0 } >> @@ -809,13 +811,15 @@ static void pirq_query_unmask(int irq) >> =C2=A0 static void eoi_pirq(struct irq_data *data) >> =C2=A0 { >> -=C2=A0=C2=A0=C2=A0 evtchn_port_t evtchn =3D evtchn_from_irq(data->irq= ); >> +=C2=A0=C2=A0=C2=A0 struct irq_info *info =3D info_for_irq(data->irq);= >> +=C2=A0=C2=A0=C2=A0 evtchn_port_t evtchn =3D info ? info->evtchn : 0; >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 struct physdev_eoi eoi =3D { .irq =3D p= irq_from_irq(data->irq) }; >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 int rc =3D 0; >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (!VALID_EVTCHN(evtchn)) >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return; >> +=C2=A0=C2=A0=C2=A0 smp_store_release(&info->is_active, 0); >=20 > Would you mind to explain why you are using the release semantics? It is basically releasing a lock. So release semantics seem to be appropriate. > It is also not clear to me if there are any expected ordering between=20 > clearing is_active and clearing the pending bit. No, I don't think there is a specific ordering required. is_active is just guarding against two simultaneous IRQ handler calls for the same event being active. Clearing the pending bit is not part of the guarded section. >=20 >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 clear_evtchn(evtchn); >=20 >=20 > The 2 lines here seems to be a common pattern in this patch. So I would= =20 > suggest to create a new helper. Okay. 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