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[23.128.96.18]) by mx.google.com with ESMTP id cf7si7493190ejb.470.2021.02.15.01.14.03; Mon, 15 Feb 2021 01:14:27 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230094AbhBOJJy (ORCPT + 99 others); Mon, 15 Feb 2021 04:09:54 -0500 Received: from mail.kernel.org ([198.145.29.99]:43426 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229595AbhBOJJu (ORCPT ); Mon, 15 Feb 2021 04:09:50 -0500 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 83D8F64E51; Mon, 15 Feb 2021 09:09:09 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1lBZsR-00EEeT-7d; Mon, 15 Feb 2021 09:09:07 +0000 Date: Mon, 15 Feb 2021 09:08:56 +0000 Message-ID: <87v9atpujb.wl-maz@kernel.org> From: Marc Zyngier To: Saravana Kannan Cc: Guenter Roeck , Rob Herring , Frank Rowand , Greg Kroah-Hartman , linux-tegra , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , LKML , Linus Walleij , Bartosz Golaszewski , Geert Uytterhoeven , Jon Hunter , Kevin Hilman , Android Kernel Team , Rob Herring , Thierry Reding Subject: Re: [PATCH v2 2/2] of: property: Add fw_devlink support for interrupts In-Reply-To: References: <20210121225712.1118239-1-saravanak@google.com> <20210121225712.1118239-3-saravanak@google.com> <20210213185422.GA195733@roeck-us.net> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: saravanak@google.com, linux@roeck-us.net, robh+dt@kernel.org, frowand.list@gmail.com, gregkh@linuxfoundation.org, linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linus.walleij@linaro.org, bgolaszewski@baylibre.com, geert@linux-m68k.org, jonathanh@nvidia.com, khilman@baylibre.com, kernel-team@android.com, robh@kernel.org, treding@nvidia.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Saravana, On Mon, 15 Feb 2021 08:29:53 +0000, Saravana Kannan wrote: > > On Sun, Feb 14, 2021 at 7:58 PM Guenter Roeck wrote: > > > > On 2/14/21 1:12 PM, Saravana Kannan wrote: > > [ ... ] > > > > > > Can you please give me the following details: > > > * The DTS file for the board (not the SoC). > > > > The devicetree file extracted from the running system is attached. > > Hope it helps. > > Hi Guenter, > > Thanks for the DTS file and logs. That helps a lot. > > Looking at the attachment and this line from the earlier email: > [ 14.084606][ T11] pci 0005:01:00.0: probe deferral - wait for > supplier interrupt-controller@0 > > It's clear the PCI node is waiting on: > interrupt-controller@0 { > #address-cells = <0x00>; > device_type = "PowerPC-Interrupt-Source-Controller"; > compatible = "ibm,opal-xive-vc\0IBM,opal-xics"; > #interrupt-cells = <0x02>; > reg = <0x00 0x00 0x00 0x00>; > phandle = <0x804b>; > interrupt-controller; > }; > > If I grep for "ibm,opal-xive-vc", I see only one instance of it in the > code. And that eventually ends up getting called like this: > irq_find_matching_fwspec() -> xive_irq_domain_match() -> xive_native_match() > > static bool xive_native_match(struct device_node *node) > { > return of_device_is_compatible(node, "ibm,opal-xive-vc"); > } > > However, when the IRQ domain are first registered, in xive_init_host() > the "np" passed in is NOT the same node that xive_native_match() would > match. > static void __init xive_init_host(struct device_node *np) > { > xive_irq_domain = irq_domain_add_nomap(np, XIVE_MAX_IRQ, > &xive_irq_domain_ops, NULL); > if (WARN_ON(xive_irq_domain == NULL)) > return; > irq_set_default_host(xive_irq_domain); > } > > Instead, the "np" here is: > interrupt-controller@6030203180000 { > ibm,xive-provision-page-size = <0x10000>; > ibm,xive-eq-sizes = <0x0c 0x10 0x15 0x18>; > single-escalation-support; > ibm,xive-provision-chips = <0x00>; > ibm,xive-#priorities = <0x08>; > compatible = "ibm,opal-xive-pe\0ibm,opal-intc"; > reg = <0x60302 0x3180000 0x00 0x10000 0x60302 > 0x3190000 0x00 0x10000 0x60302 0x31a0000 0x00 0x10000 0x60302 > 0x31b0000 0x00 0x10000>; > phandle = <0x8051>; > }; > > There are many ways to fix this, but I first want to make sure this is > a valid way to register irqdomains before trying to fix it. I just > find it weird that the node that's registered is unrelated (not a > parent/child) of the node that matches. > > Marc, > > Is this a valid way to register irqdomains? Just registering > interrupt-controller@6030203180000 DT node where there are multiple > interrupt controllers? Absolutely. The node is only one of the many possible ways to retrieve a domain. In general, what you pass as the of_node/fwnode_handle can be anything you want. It doesn't have to represent anything in the system (we even create then ex-nihilo in some cases), and the match/select callbacks are authoritative when they exist. There is also the use of a default domain, which is used as a fallback when no domain is found via the normal matching procedure. PPC has established a way of dealing with domains long before ARM did, closer to the board files of old than what we would do today (code driven rather than data structure driven). Strictly mapping domains onto HW blocks is a desirable property, but that is all it is. That doesn't affect the very purpose of the IRQ domains, which is to translate numbers from one context into another. I'd be all for rationalising this, but it is pretty hard to introduce semantic where there is none. Thanks, M. -- Without deviation from the norm, progress is not possible.