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From:   Alex Deucher <alexdeucher@gmail.com>
Date:   Mon, 15 Feb 2021 13:51:17 -0500
Message-ID: <CADnq5_MTPKXA_1G+=zVVH+G3Eqs-DZGH_2pW0=uUT0SMHbs5HQ@mail.gmail.com>
Subject: Re: [PATCH][next] drm/amd/display: Fix potential integer overflow
To:     "Gustavo A. R. Silva" <gustavoars@kernel.org>
Cc:     Harry Wentland <harry.wentland@amd.com>,
        Leo Li <sunpeng.li@amd.com>,
        Alex Deucher <alexander.deucher@amd.com>,
        =?UTF-8?Q?Christian_K=C3=B6nig?= <christian.koenig@amd.com>,
        David Airlie <airlied@linux.ie>,
        Daniel Vetter <daniel@ffwll.ch>, Huang Rui <ray.huang@amd.com>,
        Anson Jacob <Anson.Jacob@amd.com>, Lang Yu <Lang.Yu@amd.com>,
        Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>,
        Maling list - DRI developers 
        <dri-devel@lists.freedesktop.org>,
        amd-gfx list <amd-gfx@lists.freedesktop.org>,
        LKML <linux-kernel@vger.kernel.org>
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On Wed, Feb 10, 2021 at 4:23 PM Gustavo A. R. Silva
<gustavoars@kernel.org> wrote:
>
> Fix potential integer overflow by casting actual_calculated_clock_100hz
> to u64, in order to give the compiler complete information about the
> proper arithmetic to use.
>
> Notice that such variable is used in a context that expects
> an expression of type u64 (64 bits, unsigned) and the following
> expression is currently being evaluated using 32-bit arithmetic:
>
> actual_calculated_clock_100hz * post_divider
>
> Fixes: 7a03fdf628af ("drm/amd/display: fix 64bit division issue on 32bit OS")
> Addresses-Coverity-ID: 1501691 ("Unintentional integer overflow")
> Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>

Applied.  Thanks!

Alex


> ---
>  drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> index bc942725b9d8..dec58b3c42e4 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
> @@ -240,7 +240,7 @@ static bool calc_fb_divider_checking_tolerance(
>                 pll_settings->calculated_pix_clk_100hz =
>                         actual_calculated_clock_100hz;
>                 pll_settings->vco_freq =
> -                       div_u64(actual_calculated_clock_100hz * post_divider, 10);
> +                       div_u64((u64)actual_calculated_clock_100hz * post_divider, 10);
>                 return true;
>         }
>         return false;
> --
> 2.27.0
>
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