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From:   "Bedel, Alban" <alban.bedel@aerq.com>
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Subject: Re: [PATCH v2] gpio: pca953x: add support for open drain pins on
 PCAL6524
Thread-Topic: [PATCH v2] gpio: pca953x: add support for open drain pins on
 PCAL6524
Thread-Index: AQHXAJ6Y8nHh4lzybEC6MhBJ7Xlm+6pZMfQAgAHQ7QA=
Date:   Tue, 16 Feb 2021 16:37:49 +0000
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On Mon, 2021-02-15 at 14:53 +0200, Andy Shevchenko wrote:
> Hint: don't forget to include reviewers from previous version

I added you to the CC list for the new patch, did I miss someone else?

> On Thu, Feb 11, 2021 at 7:52 PM Alban Bedel <alban.bedel@aerq.com>
> wrote:
> > From a quick glance at various datasheets the PCAL6524 and the
> > PCAL6534 seems to be the only chips in this family that support
> > setting the drive mode of single pins. Other chips either don't
> > support it at all, or can only set the drive mode of whole banks,
> > which doesn't map to the GPIO API.
> >=20
> > Add a new flag, PCAL65xx_REGS, to mark chips that have the extra
> > registers needed for this feature. Then mark the needed register
> > banks
> > as readable and writable, here we don't set OUT_CONF as writable,
> > although it is, as we only need to read it. Finally add a function
> > that configures the OUT_INDCONF register when the GPIO API sets the
> > drive mode of the pins.
>=20
> ...
>=20
> > +#define PCAL65xx_REGS          BIT(10)
>=20
> Can we have it as a _TYPE, please?

Let's please take a closer look at these macros and what they mean.
Currently we have 3 possible set of functions that are indicated by
setting bits in driver_data using the PCA_xxx macros:

- Basic register only: 0
- With interrupt support: PCA_INT
- With latching interrupt regs: PCA_INT | PCA_PCAL =3D PCA_LATCH_INT

This patch then add a forth case:

- With pin config regs: PCA_INT | PCA_PCAL | $MACRO_WE_ARE_DICUSSING

Then there is the PCA953X_TYPE and PCA957X_TYPE macros which indicate
the need for a different regmap config and register layout. These are
accessed using the PCA_CHIP_TYPE() and are used as an integer value,
not as bit-field like the above ones. If we had a struct instead of a
packed integer that would be a different field.

I'll change it to PCAL65xx_TYPE if you insist, but that seems very
wrong to me to use the same naming convention for macros meant for
different fields.

>=20
> > +#define PCAL65xx_BANK_INDOUT_CONF BIT(8 + 12)
>=20
> IND is a bit ambiguous based on the description below.
> After you elaborate, I probably can propose better naming.

It's derived from the register name in the datasheet which is
"Individual pin output port X configuration register".

> > + *   - PCAL65xx with individual pin configuration
> > + *     Individual pin output config    0x40 + 12 * bank_size   RW
>=20
> Not sure I understand what "individual" means here (no, I haven't
> looked into the datasheet).

"individual" mean that each pin can be configured individually as
opposed to other chips that only allow to configure a whole bank of
pins.

> > +       if (config =3D=3D PIN_CONFIG_DRIVE_OPEN_DRAIN)
> > +               val =3D mask;
> > +       else if (config =3D=3D PIN_CONFIG_DRIVE_PUSH_PULL)
> > +               val =3D 0;
> > +       else
> > +               return -EINVAL;
>=20
> Switch-case will look more naturally here (despite being longer in
> terms of LOCs).

Ok.


> > +exit:
>=20
> exit_unlock:

Will do.

> > +       mutex_unlock(&chip->i2c_lock);
> > +       return ret;
>=20
> ...
>=20
> > +#define OF_L65XX(__nrgpio) OF_953X(__nrgpio, PCA_LATCH_INT |
> > PCAL65xx_REGS)
>=20
> When you change to the type, it will go accordingly. Don't add
> LATCH_INT to the macro.

As explained above all chips with these registers also have the
registers indicated by PCA_LATCH_INT.

Alban

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