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From:   Min Li <min.li.xe@renesas.com>
To:     Arnd Bergmann <arnd@kernel.org>
CC:     Derek Kiernan <derek.kiernan@xilinx.com>,
        Dragan Cvetic <dragan.cvetic@xilinx.com>,
        Arnd Bergmann <arnd@arndb.de>,
        gregkh <gregkh@linuxfoundation.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Networking <netdev@vger.kernel.org>,
        Richard Cochran <richardcochran@gmail.com>
Subject: RE: [PATCH net-next] misc: Add Renesas Synchronization Management
 Unit (SMU) support
Thread-Topic: [PATCH net-next] misc: Add Renesas Synchronization Management
 Unit (SMU) support
Thread-Index: AQHXACKOoFb+ofRp20OhBYk2S05d7KpS86SAgADGlHCAAIcoAIAAassggABEPICABhmmwIAAPsuAgAAOzaA=
Date:   Tue, 16 Feb 2021 22:14:21 +0000
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>=20
> I can't help but think you are evading my question I asked. If there is n=
o
> specific action that this pcm4l tool needs to perform, then I'd think we
> should better not provide any interface for it at all.
>=20
> I also found a reference to only closed source software at
> https://www.renesas.com/us/en/software-tool/ptp-clock-manager-linux
> We don't add low-level interfaces to the kernel that are only usable by
> closed-source software.
>=20
> Once you are able to describe the requirements for what pcm4l actually
> needs from the hardware, we can start discussing what a high-level
> interface would look like that can be used to replace the your current
> interface, in a way that would work across vendors and with both pcm4l an=
d
> open-source tools that do the same job.
>=20
>       Arnd

Hi Arnd

This driver is used by pcm4l to access functionalities that cannot be acces=
sed through PHC(ptp hardware clock) interface.

All these functions are kind of specific to Renesas SMU device and I have n=
ever heard other devices offering similar functions

The 3 functions currently provided are (more to be added in the future)

- set combomode

In Telecom Boundary Clock (T-BC) and Telecom Time Slave Clock (T-TSC) appli=
cations per ITU-T G.8275.2, two DPLLs can be used:
one DPLL is configured as a DCO to synthesize PTP clocks, and the other DPL=
L is configured as an EEC(Ethernet Equipment Clock)
to generate physical layer clocks. Combo mode provides physical layer frequ=
ency support from the EEC/SEC to the PTP clock.

- read DPLL's FFO

Read fractional frequency offset (FFO) from a DPLL.=20

For a DPLL channel, a Frequency Control Word (FCW) is used to adjust the fr=
equency output of the DCO. A positive value will
increase the output frequency and a negative one will decrease the output f=
requency.

This function will read FCW first and convert it to FFO.

-read DPLL's state

The DPLLs support four primary operating modes: Free-Run, Locked, Holdover,=
 and DCO. In Free-Run mode the DPLLs synthesize
clocks based on the system clock alone. In Locked mode the DPLLs filter ref=
erence clock jitter with the selected bandwidth. Additionally
in Locked mode, the long-term output frequency accuracy is the same as the =
long-term frequency accuracy of the selected input
reference. In Holdover mode, the DPLL uses frequency data acquired while in=
 Locked mode to generate accurate frequencies when input
references are not available. In DCO mode, the DPLL control loop is opened =
and the DCO can be controlled by a PTP clock recovery
servo running on an external processor to synthesize PTP clocks.

Again, at the bottom, these function are just reading/writing certain regis=
ters through I2C/SPI interface.

I am making this driver to support pcm4l since my my company, Renesas, want=
s to abstract hw details into the kernel. But I can not figure out
how to make this universally applied interface and I find misc is the best =
place to hold driver like this. On the other hand, if you have better ideas=
,
I am all ears.

Min