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From:   ChiaWei Wang <chiawei_wang@aspeedtech.com>
To:     Andrew Jeffery <andrew@aj.id.au>, Lee Jones <lee.jones@linaro.org>
CC:     BMC-SW <BMC-SW@aspeedtech.com>,
        Haiyue Wang <haiyue.wang@linux.intel.com>,
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Subject: RE: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
Thread-Topic: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
Thread-Index: AQHW6ndtLpV90qI+i0aaOeinwbKhAKo6sL2AgCF0F+A=
Date:   Wed, 17 Feb 2021 07:40:15 +0000
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References: <20210114131622.8951-1-chiawei_wang@aspeedtech.com>
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Hi All,

Do you have update on this patch series?
Aspeed has subsequent LPC module upstream plan.
We hope that the following patches can be on the basis of the fixed LPC layout.
Thanks.

Chiawei

> -----Original Message-----
> From: Andrew Jeffery <andrew@aj.id.au>
> Sent: Wednesday, January 27, 2021 8:25 AM
> To: Lee Jones <lee.jones@linaro.org>
> Subject: Re: [PATCH v5 1/5] dt-bindings: aspeed-lpc: Remove LPC partitioning
> 
> 
> 
> On Thu, 14 Jan 2021, at 23:46, Chia-Wei, Wang wrote:
> > The LPC controller has no concept of the BMC and the Host partitions.
> > This patch fixes the documentation by removing the description on LPC
> > partitions. The register offsets illustrated in the DTS node examples
> > are also fixed to adapt to the LPC DTS change.
> >
> > Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
> 
> Any thoughts Lee? If you ack it would you be happy for the patch to go through
> the Aspeed tree?
> 
> Andrew