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Date:   Thu, 18 Feb 2021 16:04:03 +0800
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References: <20210212135725.283877-1-t.schramm@manjaro.org> <20210218075835.o43tyarpimrcwbvk@gilmour>
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Subject: Re: [PATCH] clk: sunxi-ng: v3s: add support for variable rate audio pll output
To:     Maxime Ripard <maxime@cerno.tech>,
        Tobias Schramm <t.schramm@manjaro.org>
CC:     Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
        Jernej Skrabec <jernej.skrabec@siol.net>,
        linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org
From:   Icenowy Zheng <icenowy@aosc.io>
Message-ID: <C1E55B65-370F-4875-B7D6-7CD7A82A91DD@aosc.io>
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=E4=BA=8E 2021=E5=B9=B42=E6=9C=8818=E6=97=A5 GMT+08:00 =E4=B8=8B=E5=8D=883=
:58:35, Maxime Ripard <maxime@cerno=2Etech> =E5=86=99=E5=88=B0:
>Hi,
>
>On Fri, Feb 12, 2021 at 02:57:25PM +0100, Tobias Schramm wrote:
>> Previously the variable rate audio pll output was fixed to a divider
>of
>> four=2E This is unfortunately incompatible with generating commonly
>used
>> I2S core clock rates like 24=2E576MHz from the 24MHz parent clock=2E
>> This commit adds support for arbitrary audio pll output dividers to
>fix
>> that=2E
>>=20
>> Signed-off-by: Tobias Schramm <t=2Eschramm@manjaro=2Eorg>
>
>It's not really clear to me how that would help=2E

We have introducee SDM-based accurate audio PLL on several
other SoCs=2E Some people is quite sensitive about audio-related things=2E

>
>The closest frequency we can provide for 24=2E576MHz would be 24580645
>Hz,
>with N =3D 127, M =3D 31 and P =3D 4, so it would work with what we have
>already?
>
>Maxime