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Date:   Thu, 18 Feb 2021 08:58:35 +0100
From:   Maxime Ripard <maxime@cerno.tech>
To:     Tobias Schramm <t.schramm@manjaro.org>
Cc:     Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Icenowy Zheng <icenowy@aosc.io>, Chen-Yu Tsai <wens@csie.org>,
        Jernej Skrabec <jernej.skrabec@siol.net>,
        linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH] clk: sunxi-ng: v3s: add support for variable rate audio
 pll output
Message-ID: <20210218075835.o43tyarpimrcwbvk@gilmour>
References: <20210212135725.283877-1-t.schramm@manjaro.org>
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Hi,

On Fri, Feb 12, 2021 at 02:57:25PM +0100, Tobias Schramm wrote:
> Previously the variable rate audio pll output was fixed to a divider of
> four. This is unfortunately incompatible with generating commonly used
> I2S core clock rates like 24.576MHz from the 24MHz parent clock.
> This commit adds support for arbitrary audio pll output dividers to fix
> that.
>=20
> Signed-off-by: Tobias Schramm <t.schramm@manjaro.org>

It's not really clear to me how that would help.

The closest frequency we can provide for 24.576MHz would be 24580645 Hz,
with N =3D 127, M =3D 31 and P =3D 4, so it would work with what we have
already?

Maxime

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