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Fri, 19 Feb 2021 09:19:57 +0000 Message-ID: Subject: Re: [PATCH v3 0/5] phy: phy-fsl-imx8-mipi-dphy: Add i.MX8qxp LVDS PHY mode support From: Liu Ying To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org Cc: kishon@ti.com, vkoul@kernel.org, robh+dt@kernel.org, a.hajda@samsung.com, narmstrong@baylibre.com, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@siol.net, airlied@linux.ie, daniel@ffwll.ch, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, agx@sigxcpu.org, robert.chiras@nxp.com, martin.kepplinger@puri.sm Date: Fri, 19 Feb 2021 17:18:18 +0800 In-Reply-To: <1607651182-12307-1-git-send-email-victor.liu@nxp.com> References: <1607651182-12307-1-git-send-email-victor.liu@nxp.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.36.4-0ubuntu1 Content-Transfer-Encoding: 7bit X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: SG2PR02CA0105.apcprd02.prod.outlook.com (2603:1096:4:92::21) To VI1PR04MB3983.eurprd04.prod.outlook.com (2603:10a6:803:4c::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from blueberry.ap.freescale.net (119.31.174.66) by SG2PR02CA0105.apcprd02.prod.outlook.com (2603:1096:4:92::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3868.27 via Frontend Transport; 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Vinod, Kishon, it would be nice if you may help review this. Thanks, Liu Ying On Fri, 2020-12-11 at 09:46 +0800, Liu Ying wrote: > Hi, > > This series adds i.MX8qxp LVDS PHY mode support for the Mixel PHY in the > Freescale i.MX8qxp SoC. > > The Mixel PHY is MIPI DPHY + LVDS PHY combo, which can works in either > MIPI DPHY mode or LVDS PHY mode. The PHY mode is controlled by i.MX8qxp > SCU firmware. The PHY driver would call a SCU function to configure the > mode. > > The PHY driver is already supporting the Mixel MIPI DPHY in i.MX8mq SoC, > where it appears to be a single MIPI DPHY. > > > Patch 1/5 sets PHY mode in the Northwest Logic MIPI DSI host controller > bridge driver, since i.MX8qxp SoC embeds this controller IP to support > MIPI DSI displays together with the Mixel PHY. > > Patch 2/5 allows LVDS PHYs to be configured through the generic PHY functions > and through a custom structure added to the generic PHY configuration union. > > Patch 3/5 converts mixel,mipi-dsi-phy plain text dt binding to json-schema. > > Patch 4/5 adds dt binding support for the Mixel combo PHY in i.MX8qxp SoC. > > Patch 5/5 adds the i.MX8qxp LVDS PHY mode support in the Mixel PHY driver. > > > Welcome comments, thanks. > > v2->v3: > * Improve readability of mixel_dphy_set_mode() in the Mixel PHY driver. (Guido) > * Improve the 'clock-names' property in the PHY dt binding. > > v1->v2: > * Convert mixel,mipi-dsi-phy plain text dt binding to json-schema. (Guido) > * Print invalid PHY mode in dmesg from the Mixel PHY driver. (Guido) > * Add Guido's R-b tag on the patch for the nwl-dsi drm bridge driver. > > Liu Ying (5): > drm/bridge: nwl-dsi: Set PHY mode in nwl_dsi_enable() > phy: Add LVDS configuration options > dt-bindings: phy: Convert mixel,mipi-dsi-phy to json-schema > dt-bindings: phy: mixel: mipi-dsi-phy: Add Mixel combo PHY support for > i.MX8qxp > phy: freescale: phy-fsl-imx8-mipi-dphy: Add i.MX8qxp LVDS PHY mode > support > > .../devicetree/bindings/phy/mixel,mipi-dsi-phy.txt | 29 --- > .../bindings/phy/mixel,mipi-dsi-phy.yaml | 107 ++++++++ > drivers/gpu/drm/bridge/nwl-dsi.c | 6 + > drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c | 269 ++++++++++++++++++++- > include/linux/phy/phy-lvds.h | 48 ++++ > include/linux/phy/phy.h | 4 + > 6 files changed, 423 insertions(+), 40 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt > create mode 100644 Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml > create mode 100644 include/linux/phy/phy-lvds.h >