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Date:   Fri, 19 Feb 2021 17:52:21 +0000
From:   Will Deacon <will@kernel.org>
To:     Neeraj Upadhyay <neeraju@codeaurora.org>
Cc:     catalin.marinas@arm.com, saiprakash.ranjan@codeaurora.org,
        robh@kernel.org, konrad.dybcio@somainline.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] arm64: Add part number for Arm Cortex-A78
Message-ID: <20210219175220.GB6352@willie-the-truck>
References: <1613580251-12694-1-git-send-email-neeraju@codeaurora.org>
 <20210217170612.GA4254@willie-the-truck>
 <c43d8eed-2665-9e9b-c6b5-799b5281c657@codeaurora.org>
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On Wed, Feb 17, 2021 at 11:37:04PM +0530, Neeraj Upadhyay wrote:
> 
> 
> On 2/17/2021 10:36 PM, Will Deacon wrote:
> > On Wed, Feb 17, 2021 at 10:14:11PM +0530, Neeraj Upadhyay wrote:
> > > Add the MIDR part number info for the Arm Cortex-A78.
> > > 
> > > Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
> > > ---
> > >   arch/arm64/include/asm/cputype.h | 2 ++
> > >   1 file changed, 2 insertions(+)
> > > 
> > > diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
> > > index ef5b040..3aced88 100644
> > > --- a/arch/arm64/include/asm/cputype.h
> > > +++ b/arch/arm64/include/asm/cputype.h
> > > @@ -72,6 +72,7 @@
> > >   #define ARM_CPU_PART_CORTEX_A76		0xD0B
> > >   #define ARM_CPU_PART_NEOVERSE_N1	0xD0C
> > >   #define ARM_CPU_PART_CORTEX_A77		0xD0D
> > > +#define ARM_CPU_PART_CORTEX_A78		0xD41
> > >   #define APM_CPU_PART_POTENZA		0x000
> > > @@ -109,6 +110,7 @@
> > >   #define MIDR_CORTEX_A76	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
> > >   #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
> > >   #define MIDR_CORTEX_A77	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
> > > +#define MIDR_CORTEX_A78	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78)
> > >   #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
> > >   #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
> > >   #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
> > 
> > This usually means there's an erratum to work around. What are you hiding ;)
> > 
> > Will
> > 
> 
> :) . This is needed for supporting implementation defined AMU counters in
> A78 [1]. However, there is no upstream user of it.

I don't think we should add this upstream without a user.

Will