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References: <1613681704-12539-1-git-send-email-khsieh@codeaurora.org> <161368935031.1254594.14384765673800900954@swboyd.mtv.corp.google.com> <7af07dcacd5b68087cc61e467e9c57ea@codeaurora.org>
Subject: Re: [PATCH v2 2/2] drm/msm/dp: add supported max link rate specified from dtsi
From:   Stephen Boyd <swboyd@chromium.org>
Cc:     robdclark@gmail.com, sean@poorly.run, tanmay@codeaurora.org,
        abhinavk@codeaurora.org, aravindh@codeaurora.org, airlied@linux.ie,
        daniel@ffwll.ch, linux-arm-msm@vger.kernel.org,
        dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org,
        linux-kernel@vger.kernel.org
To:     khsieh@codeaurora.org
Date:   Fri, 19 Feb 2021 14:46:41 -0800
Message-ID: <161377480166.1254594.16557636343276220817@swboyd.mtv.corp.google.com>
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Quoting khsieh@codeaurora.org (2021-02-19 08:39:38)
> On 2021-02-18 15:02, Stephen Boyd wrote:
> > Quoting Kuogee Hsieh (2021-02-18 12:55:04)
> >> Allow supported link rate to be limited to the value specified at
> >> dtsi. If it is not specified, then link rate is derived from dpcd
> >> directly. Below are examples,
> >> link-rate =3D <162000> for max link rate limited at 1.62G
> >> link-rate =3D <270000> for max link rate limited at 2.7G
> >> link-rate =3D <540000> for max link rate limited at 5.4G
> >> link-rate =3D <810000> for max link rate limited at 8.1G
> >>=20
> >> Changes in V2:
> >> -- allow supported max link rate specified from dtsi
> >=20
> > Please don't roll this into the patch that removes the limit. The
> > previous version of this patch was fine. The part that lowers the limit
> > back down should be another patch.
> >=20
> > We rejected link-rate in DT before and we should reject it upstream
> > again. As far as I can tell, the maximum link rate should be determined
> > based on the panel or the type-c port on the board. The dp controller
> > can always achieve HBR3, so limiting it at the dp controller is
> > incorrect. The driver should query the endpoints to figure out if they
> > want to limit the link rate. Is that done automatically sometimes by
> > intercepting the DPCD?
>=20
> ok, i will roll back to original patch and add the second patch for max=20
> link rate limited purpose.
> panel dpcd specified max link rate it supported.
> At driver, link rate is derived from dpcd directly since driver will try =

> to use the maximum supported link rate and less lane to save power.
> Therefore it is not possible that limit link rate base on dpcd.
> AS i understand we are going to do max link rate limitation is due to=20
> old redriver chip can not support HBR3.
> How can I acquire which type-c port on the board so that I can trigger=20
> max link rate limitation?
>=20
>=20

The driver already seems to support lowering the link rate during link
training. Can't we try to train at the highest rate and then downgrade
the link speed until it trains properly? I sort of fail to see why we
need to introduce a bunch of complexity around limiting the link rate on
certain boards if the driver can figure out that link training doesn't
work at HBR3 so it should try to train at HBR2 instead.