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From:   Chun-Kuang Hu <chunkuang.hu@kernel.org>
Date:   Mon, 22 Feb 2021 07:55:10 +0800
Message-ID: <CAAOTY_92-Kw+BFnxgQbh2zFT5hDBAF+uZe+_VgCd4NAziQ0wUg@mail.gmail.com>
Subject: Re: [PATCH v1] drm/mediatek: move page flip handle into cmdq cb
To:     Yongqiang Niu <yongqiang.niu@mediatek.com>
Cc:     CK Hu <ck.hu@mediatek.com>,
        Matthias Brugger <matthias.bgg@gmail.com>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        David Airlie <airlied@linux.ie>,
        Daniel Vetter <daniel@ffwll.ch>,
        Rob Herring <robh+dt@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>,
        DRI Development <dri-devel@lists.freedesktop.org>,
        DTML <devicetree@vger.kernel.org>,
        linux-kernel <linux-kernel@vger.kernel.org>,
        Linux ARM <linux-arm-kernel@lists.infradead.org>,
        "moderated list:ARM/Mediatek SoC support" 
        <linux-mediatek@lists.infradead.org>,
        Project_Global_Chrome_Upstream_Group@mediatek.com,
        Hsin-Yi Wang <hsinyi@chromium.org>,
        Chun-Kuang Hu <chunkuang.hu@kernel.org>
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Hi, Yongqiang:

Yongqiang Niu <yongqiang.niu@mediatek.com> =E6=96=BC 2021=E5=B9=B42=E6=9C=
=8819=E6=97=A5 =E9=80=B1=E4=BA=94 =E4=B8=8B=E5=8D=885:54=E5=AF=AB=E9=81=93=
=EF=BC=9A
>
> move page flip handle into cmdq cb
> irq callback will before cmdq flush ddp register
> into hardware, that will cause the display frame page
> flip event before it realy display out time
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 33 +++++++++++++++++++++++++++=
++----
>  1 file changed, 29 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/me=
diatek/mtk_drm_crtc.c
> index bdd37ea..bece327 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -72,6 +72,13 @@ struct mtk_crtc_state {
>         unsigned int                    pending_vrefresh;
>  };
>
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> +struct mtk_cmdq_cb_data {
> +       struct cmdq_pkt                 *cmdq_handle;
> +       struct mtk_drm_crtc             *mtk_crtc;
> +};
> +#endif
> +
>  static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c)
>  {
>         return container_of(c, struct mtk_drm_crtc, base);
> @@ -96,7 +103,6 @@ static void mtk_drm_crtc_finish_page_flip(struct mtk_d=
rm_crtc *mtk_crtc)
>
>  static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
>  {
> -       drm_crtc_handle_vblank(&mtk_crtc->base);
>         if (mtk_crtc->pending_needs_vblank) {
>                 mtk_drm_crtc_finish_page_flip(mtk_crtc);
>                 mtk_crtc->pending_needs_vblank =3D false;
> @@ -241,7 +247,19 @@ struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(stru=
ct drm_crtc *crtc,
>  #if IS_REACHABLE(CONFIG_MTK_CMDQ)
>  static void ddp_cmdq_cb(struct cmdq_cb_data data)
>  {
> -       cmdq_pkt_destroy(data.data);
> +       struct mtk_cmdq_cb_data *cb_data =3D data.data;
> +
> +       if (cb_data) {
> +               struct mtk_drm_crtc *mtk_crtc =3D cb_data->mtk_crtc;
> +
> +               if (mtk_crtc)
> +                       mtk_drm_finish_page_flip(mtk_crtc);
> +
> +               if (cb_data->cmdq_handle)
> +                       cmdq_pkt_destroy(cb_data->cmdq_handle);
> +
> +               kfree(cb_data);
> +       }
>  }
>  #endif
>
> @@ -481,13 +499,20 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_c=
rtc *mtk_crtc)
>         }
>  #if IS_REACHABLE(CONFIG_MTK_CMDQ)
>         if (mtk_crtc->cmdq_client) {
> +               struct mtk_cmdq_cb_data *cb_data;
> +
>                 mbox_flush(mtk_crtc->cmdq_client->chan, 2000);
>                 cmdq_handle =3D cmdq_pkt_create(mtk_crtc->cmdq_client, PA=
GE_SIZE);
>                 cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
>                 cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false);
>                 mtk_crtc_ddp_config(crtc, cmdq_handle);
>                 cmdq_pkt_finalize(cmdq_handle);
> -               cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handl=
e);
> +
> +               cb_data =3D kmalloc(sizeof(*cb_data), GFP_KERNEL);
> +               cb_data->cmdq_handle =3D cmdq_handle;
> +               cb_data->mtk_crtc =3D mtk_crtc;
> +
> +               cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cb_data);
>         }
>  #endif
>         mutex_unlock(&mtk_crtc->hw_lock);
> @@ -674,7 +699,7 @@ void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct m=
tk_ddp_comp *comp)
>  #endif
>                 mtk_crtc_ddp_config(crtc, NULL);
>
> -       mtk_drm_finish_page_flip(mtk_crtc);
> +       drm_crtc_handle_vblank(&mtk_crtc->base);

For CPU and shadow register case, where to handle page flip?
The correct sequence should be:

1. set pending_needs_vblank to true
2. mtk_drm_crtc_hw_config
3. irq comes, handle page flip, and set pending_needs_vblank to false

But now irq comes before 2, so this patch want to fix this bug.
I think shadow register also have this problem. The control flow of
shadow register is similar to cmdq, so I would like to fix both
problem in the same way.

Regards,
Chun-Kuang.

>  }
>
>  static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc,
> --
> 1.8.1.1.dirty
>