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[124.98.97.188]) by smtp.googlemail.com with ESMTPSA id n10sm20135169pgk.91.2021.02.22.22.19.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Feb 2021 22:19:20 -0800 (PST) From: Daniel Palmer To: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, soc@kernel.org, sboyd@kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, w@1wt.eu, Daniel Palmer Subject: [PATCH 3/8] ARM: mstar: Add cpupll to base dtsi Date: Tue, 23 Feb 2021 15:18:25 +0900 Message-Id: <20210223061830.1913700-4-daniel@0x0f.com> X-Mailer: git-send-email 2.30.0.rc2 In-Reply-To: <20210223061830.1913700-1-daniel@0x0f.com> References: <20210223061830.1913700-1-daniel@0x0f.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org All MStar/SigmaStar ARMv7 SoCs have the CPU PLL at the same place so add it to the base dtsi. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-v7.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 075d583d6f40..d323c1a3f3c2 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -132,6 +132,13 @@ mpll: mpll@206000 { clocks = <&xtal>; }; + cpupll: cpupll@206400 { + compatible = "mstar,msc313-cpupll"; + reg = <0x206400 0x200>; + #clock-cells = <0>; + clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>; + }; + gpio: gpio@207800 { #gpio-cells = <2>; reg = <0x207800 0x200>; -- 2.30.0.rc2