Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: quoted-printable
In-Reply-To: <1613114930-1661-7-git-send-email-rnayak@codeaurora.org>
References: <1613114930-1661-1-git-send-email-rnayak@codeaurora.org> <1613114930-1661-7-git-send-email-rnayak@codeaurora.org>
Subject: Re: [PATCH 06/13] arm64: dts: qcom: SC7280: Add rpmhcc clock controller node
From:   Stephen Boyd <swboyd@chromium.org>
Cc:     linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org,
        Rajendra Nayak <rnayak@codeaurora.org>,
        Taniya Das <tdas@codeaurora.org>
To:     Rajendra Nayak <rnayak@codeaurora.org>, agross@kernel.org,
        bjorn.andersson@linaro.org, robh+dt@kernel.org
Date:   Mon, 22 Feb 2021 23:43:05 -0800
Message-ID: <161406618557.1254594.15985584772106947706@swboyd.mtv.corp.google.com>
User-Agent: alot/0.9.1
Precedence: bulk

Quoting Rajendra Nayak (2021-02-11 23:28:43)
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/q=
com/sc7280.dtsi
> index 7848e88..10851e7 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -6,6 +6,7 @@
>   */
> =20
>  #include <dt-bindings/clock/qcom,gcc-sc7280.h>
> +#include <dt-bindings/clock/qcom,rpmh.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> =20
> @@ -29,6 +30,42 @@
>                         clock-frequency =3D <32000>;
>                         #clock-cells =3D <0>;
>                 };
> +
> +               pcie_0_pipe_clk: pcie-0-pipe-clk {
> +                       compatible =3D "fixed-clock";
> +                       clock-frequency =3D <1000>;
> +                       #clock-cells =3D <0>;
> +               };
> +
> +               pcie_1_pipe_clk: pcie-1-pipe-clk {
> +                       compatible =3D "fixed-clock";
> +                       clock-frequency =3D <1000>;
> +                       #clock-cells =3D <0>;
> +               };
> +
> +               ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0-clk {
> +                       compatible =3D "fixed-clock";
> +                       clock-frequency =3D <1000>;
> +                       #clock-cells =3D <0>;
> +               };
> +
> +               ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1-clk {
> +                       compatible =3D "fixed-clock";
> +                       clock-frequency =3D <1000>;
> +                       #clock-cells =3D <0>;
> +               };
> +
> +               ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0-clk {
> +                       compatible =3D "fixed-clock";
> +                       clock-frequency =3D <1000>;
> +                       #clock-cells =3D <0>;
> +               };
> +
> +               usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc=
-usb30-pipe-clk {
> +                       compatible =3D "fixed-clock";
> +                       clock-frequency =3D <1000>;
> +                       #clock-cells =3D <0>;
> +               };

Shouldn't these come from the phys? Why are they being added here?

>         };
> =20
>         reserved_memory: reserved-memory {
> @@ -174,6 +211,17 @@
>                 gcc: clock-controller@100000 {
>                         compatible =3D "qcom,gcc-sc7280";
>                         reg =3D <0 0x00100000 0 0x1f0000>;
> +                       clocks =3D <&rpmhcc RPMH_CXO_CLK>,
> +                                <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
> +                                <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>,
> +                                <&ufs_phy_rx_symbol_0_clk>, <&ufs_phy_rx=
_symbol_1_clk>,
> +                                <&ufs_phy_tx_symbol_0_clk>,
> +                                <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;

If the phys aren't ready then <0> should work. Unless something goes
wrong?

> +                       clock-names =3D "bi_tcxo", "bi_tcxo_ao", "sleep_c=
lk",
> +                                     "pcie_0_pipe_clk", "pcie_1_pipe-clk=
",
> +                                     "ufs_phy_rx_symbol_0_clk", "ufs_phy=
_rx_symbol_1_clk",
> +                                     "ufs_phy_tx_symbol_0_clk",
> +                                     "usb3_phy_wrapper_gcc_usb30_pipe_cl=
k";
>                         #clock-cells =3D <1>;
>                         #reset-cells =3D <1>;
>                         #power-domain-cells =3D <1>;
> @@ -325,6 +373,13 @@
>                                           <SLEEP_TCS   3>,
>                                           <WAKE_TCS    3>,
>                                           <CONTROL_TCS 1>;
> +
> +                       rpmhcc: qcom,rpmhcc {

rpmhcc: clock-controller {

> +                               compatible =3D "qcom,sc7280-rpmh-clk";
> +                               clocks =3D <&xo_board>;
> +                               clock-names =3D "xo";
> +                               #clock-cells =3D <1>;
> +                       };
>                 };
>         };
>