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Subject: Re: [PATCH 05/13] arm64: dts: qcom: sc7280: Add RSC and PDC devices
From:   Stephen Boyd <swboyd@chromium.org>
Cc:     linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, Maulik Shah <mkshah@codeaurora.org>,
        Rajendra Nayak <rnayak@codeaurora.org>
To:     Rajendra Nayak <rnayak@codeaurora.org>, agross@kernel.org,
        bjorn.andersson@linaro.org, robh+dt@kernel.org
Date:   Mon, 22 Feb 2021 23:41:07 -0800
Message-ID: <161406606714.1254594.8318028410661523068@swboyd.mtv.corp.google.com>
User-Agent: alot/0.9.1
Precedence: bulk

Quoting Rajendra Nayak (2021-02-11 23:28:42)
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/q=
com/sc7280.dtsi
> index 1fe2eba..7848e88 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -7,6 +7,7 @@
> =20
>  #include <dt-bindings/clock/qcom,gcc-sc7280.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
> =20
>  / {
>         interrupt-parent =3D <&intc>;
> @@ -30,6 +31,18 @@
>                 };
>         };
> =20
> +       reserved_memory: reserved-memory {
> +               #address-cells =3D <2>;
> +               #size-cells =3D <2>;
> +               ranges;
> +
> +               aop_cmd_db_mem: memory@80860000 {
> +                       reg =3D <0x0 0x80860000 0x0 0x20000>;
> +                       compatible =3D "qcom,cmd-db";
> +                       no-map;
> +               };
> +       };
> +
>         cpus {
>                 #address-cells =3D <2>;
>                 #size-cells =3D <0>;
> @@ -189,6 +202,19 @@
>                         };
>                 };
> =20
> +               pdc: interrupt-controller@b220000 {
> +                       compatible =3D "qcom,sc7280-pdc", "qcom,pdc";
> +                       reg =3D <0 0xb220000 0 0x30000>;

Can you pad out reg to 8 digits? 0x0b220000

> +                       qcom,pdc-ranges =3D <0 480 40>, <40 140 14>, <54 =
263 1>,
> +                                         <55 306 4>, <59 312 3>, <62 374=
 2>,
> +                                         <64 434 2>, <66 438 3>, <69 86 =
1>,
> +                                         <70 520 54>, <124 609 31>, <155=
 63 1>,
> +                                         <156 716 12>;
> +                       #interrupt-cells =3D <2>;
> +                       interrupt-parent =3D <&intc>;
> +                       interrupt-controller;
> +               };
> +
>                 tlmm: pinctrl@f100000 {
>                         compatible =3D "qcom,sc7280-pinctrl";
>                         reg =3D <0 0xf100000 0 0x1000000>;

The same applies to the previous patch. Sorry for missing that.

> @@ -198,6 +224,7 @@
>                         interrupt-controller;
>                         #interrupt-cells =3D <2>;
>                         gpio-ranges =3D <&tlmm 0 0 175>;
> +                       wakeup-parent =3D <&pdc>;
> =20
>                         qup_uart5_default: qup-uart5-default {
>                                 pins =3D "gpio46", "gpio47";
> @@ -282,6 +309,23 @@
>                                 status =3D "disabled";
>                         };
>                 };
> +
> +               apps_rsc: rsc@18200000 {
> +                       compatible =3D "qcom,rpmh-rsc";
> +                       reg =3D <0 0x18200000 0 0x10000>,
> +                             <0 0x18210000 0 0x10000>,
> +                             <0 0x18220000 0 0x10000>;
> +                       reg-names =3D "drv-0", "drv-1", "drv-2";
> +                       interrupts =3D <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> +                       qcom,tcs-offset =3D <0xd00>;
> +                       qcom,drv-id =3D <2>;
> +                       qcom,tcs-config =3D <ACTIVE_TCS  2>,
> +                                         <SLEEP_TCS   3>,
> +                                         <WAKE_TCS    3>,
> +                                         <CONTROL_TCS 1>;
> +               };
>         };