Received: by 2002:a05:6a10:8c0a:0:0:0:0 with SMTP id go10csp2490158pxb; Tue, 23 Feb 2021 08:15:21 -0800 (PST) X-Google-Smtp-Source: ABdhPJyj5Y31+u1frR9hMVn+REc1XvhvkR7xLYR/+uaPPxkCaAFSzsdl9L7dTMRVCDKQacWrCXS8 X-Received: by 2002:a17:906:39c6:: with SMTP id i6mr27682718eje.433.1614096921722; Tue, 23 Feb 2021 08:15:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614096921; cv=none; d=google.com; s=arc-20160816; b=E+MRP22VgXU+6cwbOBs5QI5TNwrwuYs21xoqLlRZVwRyW7sQNP8bYRlv6JrfzoAo2d nCU9RqPDvsaLnMB5n4VxcZH7xx+d+xspLfWkVMa+ocN4+jfrSTfzgsyITIzcZ/lQgVRH EYGVbS2Xi3rS1DmUSIVQzkZf0V0WOek7sokqDVsQW/nZvylfSDipP22IZfrCVcBUsJ3P vGMgtmqL+kkgYmRV9BcLCyDwt5ad0DcR83YPd/nKTiJmB1ef9nw2I/k8ts7Ps5e8aCdK 27MTRqIW9kApZq3dA08AIHyxnMvLRFa+nvgw9rYpTqpZoXtCgMhpQPAwYO+m+LUH2evZ vgrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :organization:references:in-reply-to:message-id:subject:cc:to:from :date; bh=Zy3MJdJ2amo3NyM7LOvd/CAAqbOijmGBE+L4WUIWRdk=; b=om0hQ8Et4FRNTek3reVsQdWkqdYyvxoPc6RzMyt6dy1dSy6prqd+CEeF1Yui4wGjpB pnTrNYp/N2A6JWRTA7zONuD559DhAxbeQpUXGHC02geHJNHmFWGZ4I3yxg8FU+aHID9N f7HL6YvfZ0H0l5WV2TY+Ce2vvkQQpC1k2sLCfS5uXod61Z8hniplFr7xMhNU3QCmUixf MZREO6YXmTi8maMKUDwdvzlhItQ1Z6BFJ77x0M/bJd0v3dniq+gY2lmfCeSioJEkPXH4 a/Tt/BmoUxu/IYvNJpkaFqyY3J6gDtGFgdNGe/RIH/Rc9zuOiOHKexATgozFdvipEAMz 9ZXQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id c11si6144475edy.0.2021.02.23.08.14.56; Tue, 23 Feb 2021 08:15:21 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233508AbhBWQNP convert rfc822-to-8bit (ORCPT + 99 others); Tue, 23 Feb 2021 11:13:15 -0500 Received: from relay4-d.mail.gandi.net ([217.70.183.196]:34091 "EHLO relay4-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233428AbhBWQNP (ORCPT ); Tue, 23 Feb 2021 11:13:15 -0500 X-Originating-IP: 86.210.203.113 Received: from xps13 (lfbn-tou-1-972-113.w86-210.abo.wanadoo.fr [86.210.203.113]) (Authenticated sender: miquel.raynal@bootlin.com) by relay4-d.mail.gandi.net (Postfix) with ESMTPSA id DF253E0013; Tue, 23 Feb 2021 16:12:24 +0000 (UTC) Date: Tue, 23 Feb 2021 17:12:23 +0100 From: Miquel Raynal To: Md Sadre Alam Cc: mani@kernel.org, boris.brezillon@collabora.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, sricharan@codeaurora.org Subject: Re: [PATCH] mtd: rawnand: qcom: Add helper to check last code word Message-ID: <20210223171223.53f86959@xps13> In-Reply-To: <1613975095-15550-1-git-send-email-mdalam@codeaurora.org> References: <1613975095-15550-1-git-send-email-mdalam@codeaurora.org> Organization: Bootlin X-Mailer: Claws Mail 3.17.4 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello, Md Sadre Alam wrote on Mon, 22 Feb 2021 11:54:55 +0530: > This change will add helper qcom_nandc_is_last_cw() Use the imperative form, something like: " Add the qcom_nandc_is_last_cw() helper which checks if the input cw index is the last one or not. " > which will check for last code word and return true for > last code word and false for other code word. > > Signed-off-by: Md Sadre Alam > --- > drivers/mtd/nand/raw/qcom_nandc.c | 24 +++++++++++++++--------- > 1 file changed, 15 insertions(+), 9 deletions(-) > > diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c > index ae8870ec..4189a7f 100644 > --- a/drivers/mtd/nand/raw/qcom_nandc.c > +++ b/drivers/mtd/nand/raw/qcom_nandc.c > @@ -661,6 +661,12 @@ static void nandc_set_reg(struct qcom_nand_controller *nandc, int offset, > *reg = cpu_to_le32(val); > } > > +/* Helper to check the code word, whether it is last cw or not */ > +static bool qcom_nandc_is_last_cw(struct nand_ecc_ctrl *ecc, int cw) > +{ > + return cw == (ecc->steps - 1); > +} > + > /* helper to configure address register values */ > static void set_address(struct qcom_nand_host *host, u16 column, int page) > { > @@ -1632,7 +1638,7 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip, > data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); > oob_size1 = host->bbm_size; > > - if (cw == (ecc->steps - 1)) { > + if (qcom_nandc_is_last_cw(ecc, cw)) { > data_size2 = ecc->size - data_size1 - > ((ecc->steps - 1) * 4); > oob_size2 = (ecc->steps * 4) + host->ecc_bytes_hw + > @@ -1713,7 +1719,7 @@ check_for_erased_page(struct qcom_nand_host *host, u8 *data_buf, > } > > for_each_set_bit(cw, &uncorrectable_cws, ecc->steps) { > - if (cw == (ecc->steps - 1)) { > + if (qcom_nandc_is_last_cw(ecc, cw)) { > data_size = ecc->size - ((ecc->steps - 1) * 4); > oob_size = (ecc->steps * 4) + host->ecc_bytes_hw; > } else { > @@ -1773,7 +1779,7 @@ static int parse_read_errors(struct qcom_nand_host *host, u8 *data_buf, > u32 flash, buffer, erased_cw; > int data_len, oob_len; > > - if (i == (ecc->steps - 1)) { > + if (qcom_nandc_is_last_cw(ecc, i)) { > data_len = ecc->size - ((ecc->steps - 1) << 2); > oob_len = ecc->steps << 2; > } else { > @@ -1872,7 +1878,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf, > for (i = 0; i < ecc->steps; i++) { > int data_size, oob_size; > > - if (i == (ecc->steps - 1)) { > + if (qcom_nandc_is_last_cw(ecc, i)) { > data_size = ecc->size - ((ecc->steps - 1) << 2); > oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + > host->spare_bytes; > @@ -2051,7 +2057,7 @@ static int qcom_nandc_write_page(struct nand_chip *chip, const uint8_t *buf, > for (i = 0; i < ecc->steps; i++) { > int data_size, oob_size; > > - if (i == (ecc->steps - 1)) { > + if (qcom_nandc_is_last_cw(ecc, i)) { > data_size = ecc->size - ((ecc->steps - 1) << 2); > oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + > host->spare_bytes; > @@ -2068,10 +2074,10 @@ static int qcom_nandc_write_page(struct nand_chip *chip, const uint8_t *buf, > * when ECC is enabled, we don't really need to write anything > * to oob for the first n - 1 codewords since these oob regions > * just contain ECC bytes that's written by the controller > - * itself. For the last codeword, we skip the bbm positions and > - * write to the free oob area. > + * itself. For the last codeword, we skip the bbm positions and write > + * to the free oob area. Not related change, please drop. > */ > - if (i == (ecc->steps - 1)) { > + if (qcom_nandc_is_last_cw(ecc, i)) { > oob_buf += host->bbm_size; > > write_data_dma(nandc, FLASH_BUF_ACC + data_size, > @@ -2126,7 +2132,7 @@ static int qcom_nandc_write_page_raw(struct nand_chip *chip, > data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); > oob_size1 = host->bbm_size; > > - if (i == (ecc->steps - 1)) { > + if (qcom_nandc_is_last_cw(ecc, i)) { > data_size2 = ecc->size - data_size1 - > ((ecc->steps - 1) << 2); > oob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw + Thanks, Miquèl