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[76.210.143.223]) by smtp.gmail.com with ESMTPSA id q128sm11246093pfb.51.2021.02.26.21.29.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Feb 2021 21:29:14 -0800 (PST) Date: Fri, 26 Feb 2021 21:29:14 -0800 (PST) X-Google-Original-Date: Fri, 26 Feb 2021 21:29:13 PST (-0800) Subject: Re: [PATCH] RISC-V: Enable CPU Hotplug in defconfigs In-Reply-To: <20210209054620.25005-1-anup.patel@wdc.com> CC: Paul Walmsley , aou@eecs.berkeley.edu, Atish Patra , Alistair Francis , anup@brainfault.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel From: Palmer Dabbelt To: Anup Patel Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 08 Feb 2021 21:46:20 PST (-0800), Anup Patel wrote: > The CPU hotplug support has been tested on QEMU, Spike, and SiFive > Unleashed so let's enable it by default in RV32 and RV64 defconfigs. > > Signed-off-by: Anup Patel > --- > arch/riscv/configs/defconfig | 1 + > arch/riscv/configs/rv32_defconfig | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig > index 8c3d1e451703..6c0625aa96c7 100644 > --- a/arch/riscv/configs/defconfig > +++ b/arch/riscv/configs/defconfig > @@ -17,6 +17,7 @@ CONFIG_BPF_SYSCALL=y > CONFIG_SOC_SIFIVE=y > CONFIG_SOC_VIRT=y > CONFIG_SMP=y > +CONFIG_HOTPLUG_CPU=y > CONFIG_JUMP_LABEL=y > CONFIG_MODULES=y > CONFIG_MODULE_UNLOAD=y > diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig > index 2c2cda6cc1c5..8dd02b842fef 100644 > --- a/arch/riscv/configs/rv32_defconfig > +++ b/arch/riscv/configs/rv32_defconfig > @@ -18,6 +18,7 @@ CONFIG_SOC_SIFIVE=y > CONFIG_SOC_VIRT=y > CONFIG_ARCH_RV32I=y > CONFIG_SMP=y > +CONFIG_HOTPLUG_CPU=y > CONFIG_JUMP_LABEL=y > CONFIG_MODULES=y > CONFIG_MODULE_UNLOAD=y Sorry about that. I missed a handful of things, I'll send this out tomorrow.