Received: by 2002:a05:6a10:8c0a:0:0:0:0 with SMTP id go10csp3842718pxb; Mon, 1 Mar 2021 23:10:48 -0800 (PST) X-Google-Smtp-Source: ABdhPJwJ957sh8NA0bFb0blNa0MyygmmSHypGg7+Fi2/vvaB5XfQDfR9WePga1+0cewkXfFHutNU X-Received: by 2002:aa7:c3c4:: with SMTP id l4mr10044264edr.335.1614669048225; Mon, 01 Mar 2021 23:10:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614669048; cv=none; d=google.com; s=arc-20160816; b=ttm5dASRvxZrguxi6ZTbWob8I04snMGU5pYHuG4cYKEj6bEXbIQlnozLPfgeFMeA1C czH8SQwG+hIJ62kVDA84ECu6kwRtcIU19a/WwLA2xBd05SjVhkza0+neS1PuD07f71MG XcgyEUPiuKI20Lbqz+v8rdOg4uuYEg3bKXlHqUe2DBVDRHZ1wi3dpAIrCh7hq81tS32H i8mqMpMQct//9sJ7GdFce7M4OEsd7kQ10HLqUe1iEp9WNl0FS6BVMgCHKhOPDyKyUn5U 6u+nEp/LF6ND9dDT5q8nvElo2d6IC95zY4yOD6587PkpEDMFQofB5cHvcf1LlrM9tlmk 0Nkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:content-language :in-reply-to:mime-version:user-agent:date:message-id:from:references :cc:to:subject:dkim-signature; bh=iiJdRDjWUFbp3m7znHMOgxB7I0EJzPWYd34O1BbcPEg=; b=F3WjoQdlM6WgXeIHsgekBE7yxr8+r1l0nn7jv7asDeIL8+oMyRHZfJnj2Iup+lxT0O 7Nsu4JoYGFRfwKge7T1+KXWAUmnopgXWsCuNTqr9iiOID66tOsjleMBoLIBJCfhsuRaS NvIYHHx1/mpJT+3WUK+xlI0mO7wvGA65mJ3EAVFqRhLW9+jtj1XZcNGqdmTNPcuOgiGl M5zf8w3uLiHeoSdLJTbzSa3lk7tVFkk98bW3CBkTDjszm8y2H564jcu55/8Uk4zZ2pDu 4UrLKeK7E5udd4lsIbGTm6ukm4ILgQFV5H6/z3s6IaOcO6DZ+DlyvpObMLtTuHtlXME7 TMSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AgPf59Bn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id j16si13043239ejm.573.2021.03.01.23.10.25; Mon, 01 Mar 2021 23:10:48 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AgPf59Bn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377632AbhCBAsG (ORCPT + 99 others); Mon, 1 Mar 2021 19:48:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37818 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240276AbhCASp3 (ORCPT ); Mon, 1 Mar 2021 13:45:29 -0500 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A7FBFC06178B for ; Mon, 1 Mar 2021 10:44:43 -0800 (PST) Received: by mail-wm1-x333.google.com with SMTP id n4so217253wmq.3 for ; Mon, 01 Mar 2021 10:44:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=iiJdRDjWUFbp3m7znHMOgxB7I0EJzPWYd34O1BbcPEg=; b=AgPf59Bnpu82d0gde43PZP43b+zjJ6cOmOUtiBQlKXV7J8FMsvu5MJ0IB/4qhvr6+U V0ytDEsg75YZ6tjJwzG/kNCj2kcYmdOojaL/iXwJmURqMbsqxQunb67gJXOOX4IkOCri OI5rBl09tnYy+K/rsTR6/ioA7/2aBg1mKfu07JnDJcX6jZuQo+LwBDxZCteT2ITRGpVV WqoDXixpDH6ir6NV6bWH3sdZ3StdleWjF3s5HlSY2zWynOqSaLtb8xCRIkXPDPVQ+w8L fja7CFDh+GdxyYYmvbzA5TsWUJFh5HHsAjR5X8yV930vi1vlpZMoGaM55G9+TgZd+s3o hc7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=iiJdRDjWUFbp3m7znHMOgxB7I0EJzPWYd34O1BbcPEg=; b=AlxWMsscqjqNFgIPIrc+FcnBdIwV5PGwyFveUgfPjPPjZE+3zYz6lFxwc8Iw5RxZlT qLaKBPW7KKfte2qSce0D2Y55LU7T+v54CSkiAztPAcDykZU2hap59pr6uDzu1pbIbC03 b0dEhVvKtLVKesA9PTGBao0QxkjkKsyCOqPIwihgvhoV3PidRX/H7ZtcWJ4AH6coUx1I 21OQU/mOA303vWbcWvQZkyCmWpLCXj3Pvl/eJh7ZSdTilNONtstAWBlYSkXhW8DhsT8W 8dhwb+PKW6s4ljpVVQC6r8/kPRhK/EBRlc8mlY2ZKxPBbZpDYSNdkB1IebVwx903DSqs CLCw== X-Gm-Message-State: AOAM531HvpTtk3X0ntOfrP7F1RTBbOZoon/uf7kvRSpAFeA2HIxP/jE2 c/FrzcF8z9Z9aTR0GhWBm2nr5ks3i3g1BA== X-Received: by 2002:a1c:1fc6:: with SMTP id f189mr274467wmf.68.1614624282168; Mon, 01 Mar 2021 10:44:42 -0800 (PST) Received: from [192.168.0.41] (lns-bzn-59-82-252-144-192.adsl.proxad.net. [82.252.144.192]) by smtp.googlemail.com with ESMTPSA id p16sm13286308wrt.54.2021.03.01.10.44.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 01 Mar 2021 10:44:41 -0800 (PST) Subject: Re: [PATCH v2 10/10] clocksource/drivers/hyper-v: Move handling of STIMER0 interrupts To: Michael Kelley , sthemmin@microsoft.com, kys@microsoft.com, wei.liu@kernel.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, arnd@arndb.de, linux-hyperv@vger.kernel.org Cc: linux-kernel@vger.kernel.org, x86@kernel.org, linux-arch@vger.kernel.org References: <1614561332-2523-1-git-send-email-mikelley@microsoft.com> <1614561332-2523-11-git-send-email-mikelley@microsoft.com> From: Daniel Lezcano Message-ID: Date: Mon, 1 Mar 2021 19:44:40 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <1614561332-2523-11-git-send-email-mikelley@microsoft.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 01/03/2021 02:15, Michael Kelley wrote: > STIMER0 interrupts are most naturally modeled as per-cpu IRQs. But > because x86/x64 doesn't have per-cpu IRQs, the core STIMER0 interrupt > handling machinery is done in code under arch/x86 and Linux IRQs are > not used. Adding support for ARM64 means adding equivalent code > using per-cpu IRQs under arch/arm64. > > A better model is to treat per-cpu IRQs as the normal path (which it is > for modern architectures), and the x86/x64 path as the exception. Do this > by incorporating standard Linux per-cpu IRQ allocation into the main > SITMER0 driver code, and bypass it in the x86/x64 exception case. For > x86/x64, special case code is retained under arch/x86, but no STIMER0 > interrupt handling code is needed under arch/arm64. > > No functional change. > > Signed-off-by: Michael Kelley > --- > arch/x86/hyperv/hv_init.c | 2 +- > arch/x86/include/asm/mshyperv.h | 4 - > arch/x86/kernel/cpu/mshyperv.c | 10 +-- > drivers/clocksource/hyperv_timer.c | 180 ++++++++++++++++++++++++++----------- > include/asm-generic/mshyperv.h | 5 -- > include/clocksource/hyperv_timer.h | 3 +- > 6 files changed, 132 insertions(+), 72 deletions(-) > > diff --git a/arch/x86/hyperv/hv_init.c b/arch/x86/hyperv/hv_init.c > index 9af4f8a..9d10025 100644 > --- a/arch/x86/hyperv/hv_init.c > +++ b/arch/x86/hyperv/hv_init.c > @@ -327,7 +327,7 @@ static void __init hv_stimer_setup_percpu_clockev(void) > * Ignore any errors in setting up stimer clockevents > * as we can run with the LAPIC timer as a fallback. > */ > - (void)hv_stimer_alloc(); > + (void)hv_stimer_alloc(false); > > /* > * Still register the LAPIC timer, because the direct-mode STIMER is > diff --git a/arch/x86/include/asm/mshyperv.h b/arch/x86/include/asm/mshyperv.h > index 5433312..6d4891b 100644 > --- a/arch/x86/include/asm/mshyperv.h > +++ b/arch/x86/include/asm/mshyperv.h > @@ -31,10 +31,6 @@ static inline u64 hv_get_register(unsigned int reg) > > void hyperv_vector_handler(struct pt_regs *regs); > > -static inline void hv_enable_stimer0_percpu_irq(int irq) {} > -static inline void hv_disable_stimer0_percpu_irq(int irq) {} > - > - > #if IS_ENABLED(CONFIG_HYPERV) > extern int hyperv_init_cpuhp; > > diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c > index 41fd84a..cebed53 100644 > --- a/arch/x86/kernel/cpu/mshyperv.c > +++ b/arch/x86/kernel/cpu/mshyperv.c > @@ -90,21 +90,17 @@ void hv_remove_vmbus_handler(void) > set_irq_regs(old_regs); > } > > -int hv_setup_stimer0_irq(int *irq, int *vector, void (*handler)(void)) > +/* For x86/x64, override weak placeholders in hyperv_timer.c */ > +void hv_setup_stimer0_handler(void (*handler)(void)) > { > - *vector = HYPERV_STIMER0_VECTOR; > - *irq = -1; /* Unused on x86/x64 */ > hv_stimer0_handler = handler; > - return 0; > } > -EXPORT_SYMBOL_GPL(hv_setup_stimer0_irq); > > -void hv_remove_stimer0_irq(int irq) > +void hv_remove_stimer0_handler(void) > { > /* We have no way to deallocate the interrupt gate */ > hv_stimer0_handler = NULL; > } > -EXPORT_SYMBOL_GPL(hv_remove_stimer0_irq); > > void hv_setup_kexec_handler(void (*handler)(void)) > { > diff --git a/drivers/clocksource/hyperv_timer.c b/drivers/clocksource/hyperv_timer.c > index cdb8e0c..b2bf5e5 100644 > --- a/drivers/clocksource/hyperv_timer.c > +++ b/drivers/clocksource/hyperv_timer.c > @@ -18,6 +18,9 @@ > #include > #include > #include > +#include > +#include > +#include > #include > #include > #include > @@ -43,14 +46,13 @@ > */ > static bool direct_mode_enabled; > > -static int stimer0_irq; > -static int stimer0_vector; > +static int stimer0_irq = -1; > +static long __percpu *stimer0_evt; Why not static DEFINE_PER_CPU(long, stimer0_evt); no need of allocation /free ? -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog