Received: by 2002:a05:6a10:8c0a:0:0:0:0 with SMTP id go10csp4416514pxb; Tue, 2 Mar 2021 14:57:30 -0800 (PST) X-Google-Smtp-Source: ABdhPJzhqeKgsRLRZJ9Pwpou8VMiK8C4t3Jb9ynFakkOizRT+olavAF2Tb6A3sx01kGbCydSuIdN X-Received: by 2002:a50:eb97:: with SMTP id y23mr11627773edr.170.1614725850623; Tue, 02 Mar 2021 14:57:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1614725850; cv=none; d=google.com; s=arc-20160816; b=c6t0QWY6Lbt9ccDBmVNz0oUCT9fT1QIvSmHVNNL7NUyXxkuylI2J0Cw76NPm8G4lPT Pc/0Ol3GMmDZEePlG8Sgu0VMlQx7gFgcQ9FjamQ/OtftxlxYRUUKBskdujMPWbhLZvKk sz57DNKn3r29jOkcQdkH1S/Rwxuab2oUUuMlgVhtD+A0KJyQCBOdZbRkBxTtfmAt+SYA nGLPNet7liadZjjVFLYOBZB1Q2FjRT9I31GOEWBPbCJQcLrT9rKKQogEW4j4wySqAO+1 JMdIcmz21gdweRsds4cjySc90g3rjtltijUGOgvwv7nRmB1MTfG0MbPrNoKa6qVgpy5r 4lug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=u6t/37IyVxin5Ht2dpG96JWylVJHChqoPdK9b3/r2Tk=; b=iTvkezh1Rw0GRZJxc3Nr9xcgIZdX/4KdKmUAxT+4WpZkOyVb5EAuHmpThax0iYUlHX q8xKaV8CXcM0jD8Kj/0qtdtCcxTlUejyrxdJZdJeDKgJqOhI7OUDPZcSBh+p42LdtW8d m3iM450ax9/EPaKzftpaym8AH5fZ8DjHNKzrXdgTqm0T4jcMaip7nZuG+jfeik6btesa W8zmEFpx1PmW6+z6xnPQZiJB9kFIwRoIN82Sivok/eqRsaVRkm5FM11S+Wr3YAwKxy/Y IoV6PjZncGE6OJTXz7qbB6gszbnfzfhgyCyB99MG9hVMw2aRcEgvoIb8XHWMWLyOOizQ 0W4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sifive.com header.s=google header.b=dmHcDAYF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id qu25si9715600ejb.665.2021.03.02.14.56.52; Tue, 02 Mar 2021 14:57:30 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@sifive.com header.s=google header.b=dmHcDAYF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1838772AbhCBLTW (ORCPT + 99 others); Tue, 2 Mar 2021 06:19:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49848 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349675AbhCBLDJ (ORCPT ); Tue, 2 Mar 2021 06:03:09 -0500 Received: from mail-pf1-x433.google.com (mail-pf1-x433.google.com [IPv6:2607:f8b0:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2BC81C0617AB for ; Tue, 2 Mar 2021 02:59:36 -0800 (PST) Received: by mail-pf1-x433.google.com with SMTP id i10so4425174pfk.4 for ; Tue, 02 Mar 2021 02:59:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=u6t/37IyVxin5Ht2dpG96JWylVJHChqoPdK9b3/r2Tk=; b=dmHcDAYFKLLqTOsvf5p41tbZfMnkTkQbBAs8K9RFyRZ1BWqaviEUrW6MltF8u402OJ qr9t7qF/MVuoxGJnduTffQKjYx8nbsFN6oaHDJuWZ3NOHX6NAkVsw3o4tKkX87+vLtVe 0TEQdBi7us9IB1SCjzNKuV1/CKNUv7q+xMwcqYYK4w9kr/Czggj89AE2v0Tve2wtnKZp GlwZ9G6kBho4Ct0PUXMYzQ1JyYOBFLDAst2+fEIzQNwU+wpsadnfNYKVi0WQ8zjd5I1S Kktrg+quS/UItfCItat+2Z65rMVvVrbVC11DhVqfjoaiWMYoPDZS1aXBjsTi4R2ymFjX RnSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u6t/37IyVxin5Ht2dpG96JWylVJHChqoPdK9b3/r2Tk=; b=AoGAv18/cUAOYmPcy56GiemysDeVZZrUTBAfVlwE0Ltmonr0wVpc6Mnpf12uHZ6ib7 HaAXa//UqyP6KRw2HjdsQCgsfcPe3dbiMt8gm41GOOXax8EsmI1CWIE5oxmzqUNk+z/e EkFHKZJsqK2Pdzva2FTiuHQJEGrnt/ojNt0s2BcKnwbWZKgeOa4hd6SQdw8h7kV1yKKU OiNUP97npcKoVr5LHMdcGbjSjrT6PF/5GpaJgvITAXNsflmAtthmnkKLg60g2iiDBSdD +8vEU/+M81aumQK2rGDglvE027G6GjxZvlz4ZJAdm34Wtoq8UEHylx5IP1qfBbxQqACY fRDA== X-Gm-Message-State: AOAM530lc20G1N/RqWY/FD8BWYMrrQRolFgB/TxqKH2akkKEXJvJipyQ LpcNScGGE2ChkeR30rwttjQ6Pw== X-Received: by 2002:a63:d451:: with SMTP id i17mr2445904pgj.391.1614682775713; Tue, 02 Mar 2021 02:59:35 -0800 (PST) Received: from hsinchu02.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id t26sm19500451pfq.208.2021.03.02.02.59.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Mar 2021 02:59:35 -0800 (PST) From: Greentime Hu To: greentime.hu@sifive.com, paul.walmsley@sifive.com, hes@sifive.com, erik.danie@sifive.com, zong.li@sifive.com, bhelgaas@google.com, robh+dt@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, mturquette@baylibre.com, sboyd@kernel.org, lorenzo.pieralisi@arm.com, p.zabel@pengutronix.de, alex.dewar90@gmail.com, khilman@baylibre.com, hayashi.kunihiko@socionext.com, vidyas@nvidia.com, jh80.chung@samsung.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [RFC PATCH 2/6] clk: sifive: Use reset-simple in prci driver for PCIe driver Date: Tue, 2 Mar 2021 18:59:13 +0800 Message-Id: X-Mailer: git-send-email 2.30.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org We use reset-simple in this patch so that pcie driver can use devm_reset_control_get() to get this reset data structure and use reset_control_deassert() to deassert pcie_power_up_rst_n. Signed-off-by: Greentime Hu --- drivers/clk/sifive/Kconfig | 2 ++ drivers/clk/sifive/sifive-prci.c | 14 ++++++++++++++ drivers/clk/sifive/sifive-prci.h | 4 ++++ drivers/reset/Kconfig | 3 ++- 4 files changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig index 1c14eb20c066..9132c3c4aa86 100644 --- a/drivers/clk/sifive/Kconfig +++ b/drivers/clk/sifive/Kconfig @@ -10,6 +10,8 @@ if CLK_SIFIVE config CLK_SIFIVE_PRCI bool "PRCI driver for SiFive SoCs" + select RESET_CONTROLLER + select RESET_SIMPLE select CLK_ANALOGBITS_WRPLL_CLN28HPC help Supports the Power Reset Clock interface (PRCI) IP block found in diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c index baf7313dac92..925affc6de55 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -583,7 +583,21 @@ static int sifive_prci_probe(struct platform_device *pdev) if (IS_ERR(pd->va)) return PTR_ERR(pd->va); + pd->reset.rcdev.owner = THIS_MODULE; + pd->reset.rcdev.nr_resets = PRCI_RST_NR; + pd->reset.rcdev.ops = &reset_simple_ops; + pd->reset.rcdev.of_node = pdev->dev.of_node; + pd->reset.active_low = true; + pd->reset.membase = pd->va + PRCI_DEVICESRESETREG_OFFSET; + spin_lock_init(&pd->reset.lock); + + r = devm_reset_controller_register(&pdev->dev, &pd->reset.rcdev); + if (r) { + dev_err(dev, "could not register reset controller: %d\n", r); + return r; + } r = __prci_register_clocks(dev, pd, desc); + if (r) { dev_err(dev, "could not register clocks: %d\n", r); return r; diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h index 022c67cf053c..91658a88af4e 100644 --- a/drivers/clk/sifive/sifive-prci.h +++ b/drivers/clk/sifive/sifive-prci.h @@ -11,6 +11,7 @@ #include #include +#include #include /* @@ -121,6 +122,8 @@ #define PRCI_DEVICESRESETREG_CHIPLINK_RST_N_MASK \ (0x1 << PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT) +#define PRCI_RST_NR 7 + /* CLKMUXSTATUSREG */ #define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c #define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1 @@ -221,6 +224,7 @@ */ struct __prci_data { void __iomem *va; + struct reset_simple_data reset; struct clk_hw_onecell_data hw_clks; }; diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 71ab75a46491..f094df93d911 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -173,7 +173,7 @@ config RESET_SCMI config RESET_SIMPLE bool "Simple Reset Controller Driver" if COMPILE_TEST - default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC + default ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC || RISCV help This enables a simple reset controller driver for reset lines that that can be asserted and deasserted by toggling bits in a contiguous, @@ -187,6 +187,7 @@ config RESET_SIMPLE - RCC reset controller in STM32 MCUs - Allwinner SoCs - ZTE's zx2967 family + - SiFive FU740 SoCs config RESET_STM32MP157 bool "STM32MP157 Reset Driver" if COMPILE_TEST -- 2.30.0