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[80.7.220.175]) by smtp.gmail.com with ESMTPSA id m6sm24444120wrv.73.2021.03.01.02.02.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Mar 2021 02:02:41 -0800 (PST) Date: Mon, 1 Mar 2021 10:02:39 +0000 From: Daniel Thompson To: Kiran Gunda Cc: bjorn.andersson@linaro.org, jingoohan1@gmail.com, lee.jones@linaro.org, b.zolnierkie@samsung.com, dri-devel@lists.freedesktop.org, jacek.anaszewski@gmail.com, pavel@ucw.cz, robh+dt@kernel.org, mark.rutland@arm.com, linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Gross , linux-arm-msm@vger.kernel.org, linux-fbdev@vger.kernel.org, phone-devel@vger.kernel.org Subject: Re: [PATCH V3 2/2] backlight: qcom-wled: Correct the sync_toggle sequence Message-ID: <20210301100239.orbt7km6lgjwvzii@maple.lan> References: <1614590916-27070-1-git-send-email-kgunda@codeaurora.org> <1614590916-27070-3-git-send-email-kgunda@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1614590916-27070-3-git-send-email-kgunda@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 01, 2021 at 02:58:36PM +0530, Kiran Gunda wrote: > As per the current implementation, after FSC (Full Scale Current) > and brightness update the sync bits are transitioned from set-then-clear. This does not makes sense since there are too many verbs. Set and clear are both verbs so in this context: "the code will set the bit and then the code will clear the bit". Either: s/transitioned from set-then-clear/set-then-cleared/. Or: s/transitioned from set-then-clear/using a set-then-clear approach/. > But, the FSC and brightness sync takes place during a clear-then-set > transition of the sync bits. Likewise this no longer makes sense and had also become misleading. Two changes of state, clear and then set, do not usually result in a single transition. Either: s/clear-then-set/0 to 1/ Alternatively, if you want to stick exclusively to the set/clear terminology then replace the whole quoted section with: But, the FSC and brightness sync takes place when the sync bits are set (e.g. on a rising edge). > So the hardware team recommends a > clear-then-set approach in order to guarantee such a transition > regardless of the previous register state. > > Signed-off-by: Kiran Gunda With one of each of the changes proposed above: Reviewed-by: Daniel Thompson Daniel. > --- > drivers/video/backlight/qcom-wled.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/video/backlight/qcom-wled.c b/drivers/video/backlight/qcom-wled.c > index aef52b9..19f83ac 100644 > --- a/drivers/video/backlight/qcom-wled.c > +++ b/drivers/video/backlight/qcom-wled.c > @@ -337,13 +337,13 @@ static int wled3_sync_toggle(struct wled *wled) > > rc = regmap_update_bits(wled->regmap, > wled->ctrl_addr + WLED3_SINK_REG_SYNC, > - mask, mask); > + mask, WLED3_SINK_REG_SYNC_CLEAR); > if (rc < 0) > return rc; > > rc = regmap_update_bits(wled->regmap, > wled->ctrl_addr + WLED3_SINK_REG_SYNC, > - mask, WLED3_SINK_REG_SYNC_CLEAR); > + mask, mask); > > return rc; > } > @@ -353,17 +353,17 @@ static int wled5_mod_sync_toggle(struct wled *wled) > int rc; > u8 val; > > - val = (wled->cfg.mod_sel == MOD_A) ? WLED5_SINK_REG_SYNC_MOD_A_BIT : > - WLED5_SINK_REG_SYNC_MOD_B_BIT; > rc = regmap_update_bits(wled->regmap, > wled->sink_addr + WLED5_SINK_REG_MOD_SYNC_BIT, > - WLED5_SINK_REG_SYNC_MASK, val); > + WLED5_SINK_REG_SYNC_MASK, 0); > if (rc < 0) > return rc; > > + val = (wled->cfg.mod_sel == MOD_A) ? WLED5_SINK_REG_SYNC_MOD_A_BIT : > + WLED5_SINK_REG_SYNC_MOD_B_BIT; > return regmap_update_bits(wled->regmap, > wled->sink_addr + WLED5_SINK_REG_MOD_SYNC_BIT, > - WLED5_SINK_REG_SYNC_MASK, 0); > + WLED5_SINK_REG_SYNC_MASK, val); > } > > static int wled_ovp_fault_status(struct wled *wled, bool *fault_set) > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project >