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Mon, 1 Mar 2021 17:54:54 +0000 Date: Mon, 1 Mar 2021 13:54:52 -0400 From: Jason Gunthorpe To: Alistair Popple CC: , , , , , , , , , , , Subject: Re: [PATCH v3 5/8] mm: Device exclusive memory access Message-ID: <20210301175452.GR4247@nvidia.com> References: <20210226071832.31547-1-apopple@nvidia.com> <20210226071832.31547-6-apopple@nvidia.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20210226071832.31547-6-apopple@nvidia.com> X-ClientProxiedBy: BL1PR13CA0252.namprd13.prod.outlook.com (2603:10b6:208:2ba::17) To DM6PR12MB3834.namprd12.prod.outlook.com (2603:10b6:5:14a::12) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from mlx.ziepe.ca (142.162.115.133) by BL1PR13CA0252.namprd13.prod.outlook.com (2603:10b6:208:2ba::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3912.10 via Frontend Transport; Mon, 1 Mar 2021 17:54:53 +0000 Received: from jgg by mlx with local (Exim 4.94) (envelope-from ) id 1lGmku-0033wm-Ji; Mon, 01 Mar 2021 13:54:52 -0400 X-Header: ProcessedBy-CMR-outbound DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1614621297; bh=y90lc/7CHOvq6P326uUC8A7kFIIiRlcbyV9QLh9EURk=; h=ARC-Seal:ARC-Message-Signature:ARC-Authentication-Results:Date: From:To:CC:Subject:Message-ID:References:Content-Type: Content-Disposition:In-Reply-To:X-ClientProxiedBy:MIME-Version: X-MS-Exchange-MessageSentRepresentingType:X-Header; b=dHU8QYtaDHO6367x+GB9IdYqsN0t3wVWNB9OUUjJHC5YXWQLX2JiT8rOTjF4Z0YLU vOVys3oX/MbcGavNPVP1Wg6UsswKShG3l1bjayZyVcAkdGy+3HCDaBIekysWrawt3Z 5ZUKNXxnPZOnonAILP+ROrnWrQN7YpEtj6V1pGf8p6wPVrUm8gh12mR9R8IbA2cQ87 a01HyhLLIwO2qHeWEnzSRwb8BeR1QcgYBNxfLFsbkgm92d7Hb/yO2WSmZHQR1ME4O6 9TSSTIrshgyvI+JLKFcs9CEuxf0rjPdQcYrGElsUuKR7EiIOvD5fa5sAnl39agwm0k 5mGsXvK0wTpig== Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Feb 26, 2021 at 06:18:29PM +1100, Alistair Popple wrote: > Some devices require exclusive write access to shared virtual > memory (SVM) ranges to perform atomic operations on that memory. This > requires CPU page tables to be updated to deny access whilst atomic > operations are occurring. > > In order to do this introduce a new swap entry > type (SWP_DEVICE_EXCLUSIVE). When a SVM range needs to be marked for > exclusive access by a device all page table mappings for the particular > range are replaced with device exclusive swap entries. This causes any > CPU access to the page to result in a fault. > > Faults are resovled by replacing the faulting entry with the original > mapping. This results in MMU notifiers being called which a driver uses > to update access permissions such as revoking atomic access. After > notifiers have been called the device will no longer have exclusive > access to the region. This makes alot more sense than the prior versions! I don't know the migration area especially well, but nothing caught my eye in here Jason