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From:   dillon.minfei@gmail.com
To:     robh+dt@kernel.org, mcoquelin.stm32@gmail.com,
        alexandre.torgue@st.com, devicetree@vger.kernel.org,
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        linux@armlinux.org.uk, vladimir.murzin@arm.com,
        afzal.mohd.ma@gmail.com
Cc:     dillon min <dillon.minfei@gmail.com>
Subject: [PATCH 1/8] ARM: ARMv7-M: Fix register restore corrupt after svc call
Date:   Wed,  3 Mar 2021 16:05:10 +0800
Message-Id: <1614758717-18223-2-git-send-email-dillon.minfei@gmail.com>
In-Reply-To: <1614758717-18223-1-git-send-email-dillon.minfei@gmail.com>
References: <1614758717-18223-1-git-send-email-dillon.minfei@gmail.com>
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From: dillon min <dillon.minfei@gmail.com>

For some case, kernel not boot by u-boot(single thread),
but by rtos , as most rtos use pendsv to do context switch.

So, we need add an lr check after svc call, to find out should
use psp or msp. else register restore after svc call might be
corrupted.

Fixes: b70cd406d7fe ("ARM: 8671/1: V7M: Preserve registers across switch from Thread to Handler mode")
Signed-off-by: dillon min <dillon.minfei@gmail.com>
---
 arch/arm/mm/proc-v7m.S | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
index 84459c1d31b8..c93d2757312d 100644
--- a/arch/arm/mm/proc-v7m.S
+++ b/arch/arm/mm/proc-v7m.S
@@ -137,7 +137,10 @@ __v7m_setup_cont:
 1:	cpsid	i
 	/* Calculate exc_ret */
 	orr	r10, lr, #EXC_RET_THREADMODE_PROCESSSTACK
-	ldmia	sp, {r0-r3, r12}
+	tst	lr, #EXC_RET_STACK_MASK
+	mrsne	r4, psp
+	moveq	r4, sp
+	ldmia	r4!, {r0-r3, r12}
 	str	r5, [r12, #11 * 4]	@ restore the original SVC vector entry
 	mov	lr, r6			@ restore LR
 
-- 
2.7.4