Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: quoted-printable
In-Reply-To: <f58070ee-ff00-f8c5-6459-782562e903e5@codeaurora.org>
References: <1613114930-1661-1-git-send-email-rnayak@codeaurora.org> <1613114930-1661-7-git-send-email-rnayak@codeaurora.org> <161406618557.1254594.15985584772106947706@swboyd.mtv.corp.google.com> <f58070ee-ff00-f8c5-6459-782562e903e5@codeaurora.org>
Subject: Re: [PATCH 06/13] arm64: dts: qcom: SC7280: Add rpmhcc clock controller node
From:   Stephen Boyd <swboyd@chromium.org>
Cc:     linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
To:     Rajendra Nayak <rnayak@codeaurora.org>,
        Taniya Das <tdas@codeaurora.org>, agross@kernel.org,
        bjorn.andersson@linaro.org, robh+dt@kernel.org
Date:   Wed, 03 Mar 2021 00:21:25 -0800
Message-ID: <161475968509.1478170.5248506718236838205@swboyd.mtv.corp.google.com>
User-Agent: alot/0.9.1
Precedence: bulk

Quoting Taniya Das (2021-03-01 09:27:06)
> On 2/23/2021 1:13 PM, Stephen Boyd wrote:
> > Quoting Rajendra Nayak (2021-02-11 23:28:43)
> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dt=
s/qcom/sc7280.dtsi
> >> +               usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-=
gcc-usb30-pipe-clk {
> >> +                       compatible =3D "fixed-clock";
> >> +                       clock-frequency =3D <1000>;
> >> +                       #clock-cells =3D <0>;
> >> +               };
> >=20
> > Shouldn't these come from the phys? Why are they being added here?
> >=20
>=20
> Once the phys are added, these could be replaced, that was the reason to =

> add them.
>=20
> >>          };
> >>  =20
> >>          reserved_memory: reserved-memory {
> >> @@ -174,6 +211,17 @@
> >>                  gcc: clock-controller@100000 {
> >>                          compatible =3D "qcom,gcc-sc7280";
> >>                          reg =3D <0 0x00100000 0 0x1f0000>;
> >> +                       clocks =3D <&rpmhcc RPMH_CXO_CLK>,
> >> +                                <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk=
>,
> >> +                                <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk=
>,
> >> +                                <&ufs_phy_rx_symbol_0_clk>, <&ufs_phy=
_rx_symbol_1_clk>,
> >> +                                <&ufs_phy_tx_symbol_0_clk>,
> >> +                                <&usb3_phy_wrapper_gcc_usb30_pipe_clk=
>;
> >=20
> > If the phys aren't ready then <0> should work. Unless something goes
> > wrong?
> >
>=20
> Nothing would go wrong if we add <0>, but wanted them to be replaced=20
> once the support is added.

Please use <0> to indicate that it's missing. Otherwise we may never
realize that we should connect it up later.