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Date:   Fri, 5 Mar 2021 03:46:31 +0100 (CET)
From:   "Maciej W. Rozycki" <macro@orcam.me.uk>
To:     Jiaxun Yang <jiaxun.yang@flygoat.com>
cc:     Tiezhu Yang <yangtiezhu@loongson.cn>,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        Nathan Chancellor <nathan@kernel.org>,
        Nick Desaulniers <ndesaulniers@google.com>,
        linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
        clang-built-linux@googlegroups.com,
        Xuefeng Li <lixuefeng@loongson.cn>
Subject: Re: [PATCH] MIPS: Add comment about CONFIG_MIPS32_O32 in
 loongson3_defconfig when build with Clang
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On Fri, 5 Mar 2021, Jiaxun Yang wrote:

> >   Huh?  Is that a joke?  From the o32 psABI's point of view a MIPS64 CPU is
> > exactly the same as a MIPS32 one (for whatever ISA revision), so there's
> > nothing to support there really other than the CPU/ISA name.
> 
> Clang treat MIPS32 as a different backend so we may need some extra effort....
> 
> TBH it is a toolchain issue and kernel workaround seems bogus.
> 
> From my point view we can "s/mips64r2/mips32r2" when doing syscall checks
> to workaround clang issue instead of disable it for kernel.

 I had something like this in mind, but obviously that has to be done in a 
consistent manner across all the possible 64-bit `-march=...' selections, 
as I suppose that is where the problem comes from.  So we'd have to handle 
things like say `octeon'.  But I'd like to see the invocation line to be 
sure (I could try and check that myself, but I don't have Clang and it's 
the patch submitter's job anyway to explain things and not the reviewer's 
to chase them).

 Maybe we could cheat and wire everything to a single setting so as to 
keep the hack to the minimum, but we need to know what the right setting 
is from the Clang people.

 NB only MIPS IV is special in that it has 32-bit extensions beyond MIPS 
III but not a corresponding 32-bit ISA.  The corresponding 32-bit ISA for 
MIPS III is MIPS II, and obviously all the modern MIPS ISAs come in pairs.  
So it's only MIPS IV where o32 may want special support (at the hardware 
level the ISA had the CP0.Status.XX bit to control the ISA extensions), 
and I guess only a few people care at this point, though some are present 
on this mailing list.

  Maciej