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References: <20210305120930.14297-1-mark-pk.tsai@mediatek.com>
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From:   Daniel Palmer <daniel@0x0f.com>
Date:   Sun, 7 Mar 2021 02:06:51 +0900
Message-ID: <CAFr9PXmDp7UwWnT+49Yciy-gvYiQOd3cus0W_QnGKm-LqziHCg@mail.gmail.com>
Subject: Re: [PATCH] irqchip/irq-mst: Support polarity configuration
To:     Mark-PK Tsai <mark-pk.tsai@mediatek.com>
Cc:     Marc Zyngier <maz@kernel.org>, Daniel Palmer <daniel@thingy.jp>,
        Thomas Gleixner <tglx@linutronix.de>,
        Jason Cooper <jason@lakedaemon.net>,
        Matthias Brugger <matthias.bgg@gmail.com>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
        linux-mediatek@lists.infradead.org, yj.chiang@mediatek.com
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Hi Mark-PK,

I'm trying to understand the logic behind the changes.
It seems like the polarity of interrupts is always the same between
the MStar intc and the GIC? Low level interrupts are handled in the
mstar intc and become high level interrupts to the GIC?
I think for the Mstar MSC313(e) and SigmaStar chips all of the
internal interrupts are high level so I never noticed this behaviour.
I can't remember seeing anything that handled this in the MStar kernel
code I looked at.
Is this specific to a certain chip or does it apply for everything
with this intc?
The register values being lost if the chip goes into suspend to memory
makes sense for the MStar chips too I think as everything that is not
in the "pmsleep" register group seems to be lost.

Thanks,

Daniel