Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
Date:   Sat, 6 Mar 2021 17:38:18 +0000
From:   Jonathan Cameron <jic23@kernel.org>
To:     Sean Nyekjaer <sean@geanix.com>
Cc:     Lars-Peter Clausen <lars@metafoo.de>,
        Peter Meerwald-Stadler <pmeerw@pmeerw.net>,
        linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] iio: accel: mma8452: fix indentation
Message-ID: <20210306173818.31cd17c9@archlinux>
In-Reply-To: <20210301080029.1974797-1-sean@geanix.com>
References: <20210301080029.1974797-1-sean@geanix.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: 7bit
Precedence: bulk

On Mon,  1 Mar 2021 09:00:28 +0100
Sean Nyekjaer <sean@geanix.com> wrote:

> Improve readability by fixing indentation.
> 
> Signed-off-by: Sean Nyekjaer <sean@geanix.com>
Applied.

Thanks,

Jonathan

> ---
> v2: removed fixing of register values indentation
> 
>  drivers/iio/accel/mma8452.c | 46 ++++++++++++++++++-------------------
>  1 file changed, 23 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/iio/accel/mma8452.c b/drivers/iio/accel/mma8452.c
> index b0176d936423..33f0c419d8ff 100644
> --- a/drivers/iio/accel/mma8452.c
> +++ b/drivers/iio/accel/mma8452.c
> @@ -58,7 +58,7 @@
>  #define MMA8452_FF_MT_THS			0x17
>  #define  MMA8452_FF_MT_THS_MASK			0x7f
>  #define MMA8452_FF_MT_COUNT			0x18
> -#define MMA8452_FF_MT_CHAN_SHIFT	3
> +#define MMA8452_FF_MT_CHAN_SHIFT		3
>  #define MMA8452_TRANSIENT_CFG			0x1d
>  #define  MMA8452_TRANSIENT_CFG_CHAN(chan)	BIT(chan + 1)
>  #define  MMA8452_TRANSIENT_CFG_HPF_BYP		BIT(0)
> @@ -70,7 +70,7 @@
>  #define MMA8452_TRANSIENT_THS			0x1f
>  #define  MMA8452_TRANSIENT_THS_MASK		GENMASK(6, 0)
>  #define MMA8452_TRANSIENT_COUNT			0x20
> -#define MMA8452_TRANSIENT_CHAN_SHIFT 1
> +#define MMA8452_TRANSIENT_CHAN_SHIFT		1
>  #define MMA8452_CTRL_REG1			0x2a
>  #define  MMA8452_CTRL_ACTIVE			BIT(0)
>  #define  MMA8452_CTRL_DR_MASK			GENMASK(5, 3)
> @@ -134,33 +134,33 @@ struct mma8452_data {
>    * used for different chips and the relevant registers are included here.
>    */
>  struct mma8452_event_regs {
> -		u8 ev_cfg;
> -		u8 ev_cfg_ele;
> -		u8 ev_cfg_chan_shift;
> -		u8 ev_src;
> -		u8 ev_ths;
> -		u8 ev_ths_mask;
> -		u8 ev_count;
> +	u8 ev_cfg;
> +	u8 ev_cfg_ele;
> +	u8 ev_cfg_chan_shift;
> +	u8 ev_src;
> +	u8 ev_ths;
> +	u8 ev_ths_mask;
> +	u8 ev_count;
>  };
>  
>  static const struct mma8452_event_regs ff_mt_ev_regs = {
> -		.ev_cfg = MMA8452_FF_MT_CFG,
> -		.ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
> -		.ev_cfg_chan_shift = MMA8452_FF_MT_CHAN_SHIFT,
> -		.ev_src = MMA8452_FF_MT_SRC,
> -		.ev_ths = MMA8452_FF_MT_THS,
> -		.ev_ths_mask = MMA8452_FF_MT_THS_MASK,
> -		.ev_count = MMA8452_FF_MT_COUNT
> +	.ev_cfg = MMA8452_FF_MT_CFG,
> +	.ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
> +	.ev_cfg_chan_shift = MMA8452_FF_MT_CHAN_SHIFT,
> +	.ev_src = MMA8452_FF_MT_SRC,
> +	.ev_ths = MMA8452_FF_MT_THS,
> +	.ev_ths_mask = MMA8452_FF_MT_THS_MASK,
> +	.ev_count = MMA8452_FF_MT_COUNT
>  };
>  
>  static const struct mma8452_event_regs trans_ev_regs = {
> -		.ev_cfg = MMA8452_TRANSIENT_CFG,
> -		.ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
> -		.ev_cfg_chan_shift = MMA8452_TRANSIENT_CHAN_SHIFT,
> -		.ev_src = MMA8452_TRANSIENT_SRC,
> -		.ev_ths = MMA8452_TRANSIENT_THS,
> -		.ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
> -		.ev_count = MMA8452_TRANSIENT_COUNT,
> +	.ev_cfg = MMA8452_TRANSIENT_CFG,
> +	.ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
> +	.ev_cfg_chan_shift = MMA8452_TRANSIENT_CHAN_SHIFT,
> +	.ev_src = MMA8452_TRANSIENT_SRC,
> +	.ev_ths = MMA8452_TRANSIENT_THS,
> +	.ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
> +	.ev_count = MMA8452_TRANSIENT_COUNT,
>  };
>  
>  /**