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Date:   Sat, 06 Mar 2021 18:28:20 +0000
Message-ID: <875z24rvaz.wl-maz@kernel.org>
From:   Marc Zyngier <maz@kernel.org>
To:     Daniel Palmer <daniel@0x0f.com>
Cc:     Mark-PK Tsai <mark-pk.tsai@mediatek.com>,
        Daniel Palmer <daniel@thingy.jp>,
        Thomas Gleixner <tglx@linutronix.de>,
        Jason Cooper <jason@lakedaemon.net>,
        Matthias Brugger <matthias.bgg@gmail.com>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
        linux-mediatek@lists.infradead.org, yj.chiang@mediatek.com
Subject: Re: [PATCH] irqchip/irq-mst: Support polarity configuration
In-Reply-To: <CAFr9PXmDp7UwWnT+49Yciy-gvYiQOd3cus0W_QnGKm-LqziHCg@mail.gmail.com>
References: <20210305120930.14297-1-mark-pk.tsai@mediatek.com>
        <CAFr9PXmDp7UwWnT+49Yciy-gvYiQOd3cus0W_QnGKm-LqziHCg@mail.gmail.com>
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On Sat, 06 Mar 2021 17:06:51 +0000,
Daniel Palmer <daniel@0x0f.com> wrote:
> 
> Hi Mark-PK,
> 
> I'm trying to understand the logic behind the changes.
> It seems like the polarity of interrupts is always the same between
> the MStar intc and the GIC? Low level interrupts are handled in the
> mstar intc and become high level interrupts to the GIC?

That's because the GIC only supports level-high input interrupts when
they are level triggered (and rising edge when edge triggered).

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.