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From:   "Limonciello, Mario" <Mario.Limonciello@dell.com>
To:     "David E. Box" <david.e.box@linux.intel.com>,
        "irenic.rajneesh@gmail.com" <irenic.rajneesh@gmail.com>,
        "hdegoede@redhat.com" <hdegoede@redhat.com>,
        "mgross@linux.intel.com" <mgross@linux.intel.com>,
        "sasha.neftin@intel.com" <sasha.neftin@intel.com>
CC:     "platform-driver-x86@vger.kernel.org" 
        <platform-driver-x86@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "intel-wired-lan@lists.osuosl.org" <intel-wired-lan@lists.osuosl.org>
Subject: RE: [PATCH] platform/x86: intel_pmc: Ignore GBE LTR on Tiger Lake
 platforms
Thread-Topic: [PATCH] platform/x86: intel_pmc: Ignore GBE LTR on Tiger Lake
 platforms
Thread-Index: AQHXEfLhzYLSroQh8UmKnpvnJJhjqqp6Wj0A
Date:   Mon, 8 Mar 2021 17:20:51 +0000
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References: <20210305190608.1834164-1-david.e.box@linux.intel.com>
In-Reply-To: <20210305190608.1834164-1-david.e.box@linux.intel.com>
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>=20
> [EXTERNAL EMAIL]
>=20
> Due to a HW limitation, the Latency Tolerance Reporting (LTR) value
> programmed in the Tiger Lake GBE controller is not large enough to allow
> the platform to enter Package C10, which in turn prevents the platform fr=
om
> achieving its low power target during suspend-to-idle.  Ignore the GBE LT=
R
> value on Tiger Lake. LTR ignore functionality is currently performed sole=
ly
> by a debugfs write call. Split out the LTR code into its own function tha=
t
> can be called by both the debugfs writer and by this work around.
>=20
> Signed-off-by: David E. Box <david.e.box@linux.intel.com>
> Reviewed-by: Sasha Neftin <sasha.neftin@intel.com>
> Cc: intel-wired-lan@lists.osuosl.org
> ---
>  drivers/platform/x86/intel_pmc_core.c | 55 ++++++++++++++++++++-------
>  1 file changed, 42 insertions(+), 13 deletions(-)

I feel like this driver change causes a weak reference between e1000e and i=
ntel_pmc_core.
It would mean significantly different behavior if you use e1000e but don't =
have PMC module
available for any reason.

In this case does it maybe make sense to at least use "imply" in the Kconfi=
g for e1000e so
that selecting e1000e gets intel-pmc-core enabled too?

>=20
> diff --git a/drivers/platform/x86/intel_pmc_core.c
> b/drivers/platform/x86/intel_pmc_core.c
> index ee2f757515b0..ab31eb646a1a 100644
> --- a/drivers/platform/x86/intel_pmc_core.c
> +++ b/drivers/platform/x86/intel_pmc_core.c
> @@ -863,34 +863,45 @@ static int pmc_core_pll_show(struct seq_file *s, vo=
id
> *unused)
>  }
>  DEFINE_SHOW_ATTRIBUTE(pmc_core_pll);
>=20
> -static ssize_t pmc_core_ltr_ignore_write(struct file *file,
> -					 const char __user *userbuf,
> -					 size_t count, loff_t *ppos)
> +static int pmc_core_write_ltr_ignore(u32 value)
>  {
>  	struct pmc_dev *pmcdev =3D &pmc;
>  	const struct pmc_reg_map *map =3D pmcdev->map;
> -	u32 val, buf_size, fd;
> -	int err;
> -
> -	buf_size =3D count < 64 ? count : 64;
> -
> -	err =3D kstrtou32_from_user(userbuf, buf_size, 10, &val);
> -	if (err)
> -		return err;
> +	u32 fd;
> +	int err =3D 0;
>=20
>  	mutex_lock(&pmcdev->lock);
>=20
> -	if (val > map->ltr_ignore_max) {
> +	if (fls(value) > map->ltr_ignore_max) {
>  		err =3D -EINVAL;
>  		goto out_unlock;
>  	}
>=20
>  	fd =3D pmc_core_reg_read(pmcdev, map->ltr_ignore_offset);
> -	fd |=3D (1U << val);
> +	fd |=3D value;
>  	pmc_core_reg_write(pmcdev, map->ltr_ignore_offset, fd);
>=20
>  out_unlock:
>  	mutex_unlock(&pmcdev->lock);
> +
> +	return err;
> +}
> +
> +static ssize_t pmc_core_ltr_ignore_write(struct file *file,
> +					 const char __user *userbuf,
> +					 size_t count, loff_t *ppos)
> +{
> +	u32 buf_size, val;
> +	int err;
> +
> +	buf_size =3D count < 64 ? count : 64;
> +
> +	err =3D kstrtou32_from_user(userbuf, buf_size, 10, &val);
> +	if (err)
> +		return err;
> +
> +	err =3D pmc_core_write_ltr_ignore(1U << val);
> +
>  	return err =3D=3D 0 ? count : err;
>  }
>=20
> @@ -1189,6 +1200,15 @@ static int quirk_xtal_ignore(const struct dmi_syst=
em_id
> *id)
>  	return 0;
>  }
>=20
> +static int quirk_ltr_ignore(u32 val)
> +{
> +	int err;
> +
> +	err =3D pmc_core_write_ltr_ignore(val);
> +
> +	return err;
> +}
> +
>  static const struct dmi_system_id pmc_core_dmi_table[]  =3D {
>  	{
>  	.callback =3D quirk_xtal_ignore,
> @@ -1244,6 +1264,15 @@ static int pmc_core_probe(struct platform_device *=
pdev)
>  	pmcdev->pmc_xram_read_bit =3D pmc_core_check_read_lock_bit();
>  	dmi_check_system(pmc_core_dmi_table);
>=20
> +	/*
> +	 * On TGL, due to a hardware limitation, the GBE LTR blocks PC10 when
> +	 * a cable is attached. Tell the PMC to ignore it.
> +	 */
> +	if (pmcdev->map =3D=3D &tgl_reg_map) {
> +		dev_dbg(&pdev->dev, "ignoring GBE LTR\n");
> +		quirk_ltr_ignore(1U << 3);
> +	}
> +
>  	pmc_core_dbgfs_register(pmcdev);
>=20
>  	device_initialized =3D true;
> --
> 2.25.1