Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18;
Date:   Mon, 8 Mar 2021 11:45:57 -0700
From:   Rob Herring <robh@kernel.org>
To:     Claudiu Beznea <claudiu.beznea@microchip.com>
Cc:     tglx@linutronix.de, maz@kernel.org, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        nicolas.ferre@microchip.com
Subject: Re: [PATCH 1/2] dt-bindings: mchp-eic: add bindings
Message-ID: <20210308184557.GA2768020@robh.at.kernel.org>
References: <20210302102846.619980-1-claudiu.beznea@microchip.com>
 <20210302102846.619980-2-claudiu.beznea@microchip.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <20210302102846.619980-2-claudiu.beznea@microchip.com>
Precedence: bulk

On Tue, Mar 02, 2021 at 12:28:45PM +0200, Claudiu Beznea wrote:
> Add DT bindings for Microchip External Interrupt Controller.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
>  .../interrupt-controller/mchp,eic.yaml        | 74 +++++++++++++++++++
>  1 file changed, 74 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mchp,eic.yaml
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/mchp,eic.yaml b/Documentation/devicetree/bindings/interrupt-controller/mchp,eic.yaml
> new file mode 100644
> index 000000000000..5a927817aa7d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/mchp,eic.yaml
> @@ -0,0 +1,74 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/mchp,eic.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip External Interrupt Controller
> +
> +maintainers:
> +  - Claudiu Beznea <claudiu.beznea@microchip.com>
> +
> +description:
> +  This interrupt controller is found in Microchip SoCs (SAMA7G5) and provides
> +  support for handling up to 2 external interrupt lines.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - microchip,sama7g5-eic
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupt-controller: true
> +
> +  '#interrupt-cells':
> +    const: 3
> +    description:
> +      The first cell is the input IRQ number (between 0 and 1), the second cell
> +      is the trigger type as defined in interrupt.txt present in this directory
> +      and the third cell is the glitch filter (1, 2, 4, 8) in clock cycles
> +
> +  'interrupts':

Don't need quotes here.

> +    description: |
> +      Contains the GIC SPI IRQs mapped to the external interrupt lines. They
> +      should be specified sequentially from output 0 to output 1.
> +    minItems: 2
> +    maxItems: 2
> +
> +  clocks:
> +    maxItems: 1
> +
> +  clock-names:
> +    const: pclk
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupt-controller
> +  - '#interrupt-cells'
> +  - 'interrupts'

Or here.

> +  - clocks
> +  - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/at91.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    eic: eic@e1628000 {

interrupt-controller@...

> +      compatible = "microchip,sama7g5-eic";
> +      reg = <0xe1628000 0x100>;
> +      interrupt-parent = <&gic>;
> +      interrupt-controller;
> +      #interrupt-cells = <3>;
> +      interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
> +                   <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
> +      clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
> +      clock-names = "pclk";
> +    };
> +
> +...
> -- 
> 2.25.1
>