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Tue, 9 Mar 2021 06:23:03 +0000 From: Jason Tian OS To: Shiju Jose , "linux-kernel@vger.kernel.org" , "linux-edac@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "james.morse@arm.com" , Tyler Baicar OS CC: Frank Wang Subject: RE: [PATCH v2] arm64/ras: Update code to trace out more data for ARM processor Thread-Topic: [PATCH v2] arm64/ras: Update code to trace out more data for ARM processor Thread-Index: AQHW+2Xc1/u9iv8FrUCGangWCJ9cKqpnsmUAgBOv8oA= Date: Tue, 9 Mar 2021 06:23:03 +0000 Message-ID: References: <20210205022229.313030-1-jason@os.amperecomputing.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: huawei.com; dkim=none (message not signed) header.d=none;huawei.com; dmarc=none action=none header.from=os.amperecomputing.com; x-originating-ip: [180.167.209.74] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 6d1bab64-14b6-4875-92f7-08d8e2c3cb9a x-ms-traffictypediagnostic: MW2PR0102MB3513: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:390; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MWHPR01MB2493.prod.exchangelabs.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6d1bab64-14b6-4875-92f7-08d8e2c3cb9a X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Mar 2021 06:23:03.3970 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: AcSUjqbqGmXnK/RE3EYn35sLcNw0ZbOqjBCsd2GsswsGa7rf6BqzCxSaHlp8o7hPsvxHACXh+RZLFmSZ1pyDtVBJZ5xW2zpbuX6rXAXnScBTVAWY5nrlX/CxgR9PcABm X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW2PR0102MB3513 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi All, May I know whether this patch can be merged or not? Thanks. Jason -----Original Message----- From: Shiju Jose =20 Sent: Thursday, February 25, 2021 1:44 AM To: Jason Tian OS ; linux-kernel@vger.kernel.= org; linux-edac@vger.kernel.org; linux-arm-kernel@lists.infradead.org; jame= s.morse@arm.com; Tyler Baicar OS Cc: Frank Wang Subject: RE: [PATCH v2] arm64/ras: Update code to trace out more data for A= RM processor >-----Original Message----- >From: linux-arm-kernel=20 >[mailto:linux-arm-kernel-bounces@lists.infradead.org] >On Behalf Of Jason Tian >Sent: 05 February 2021 02:22 >To: linux-kernel@vger.kernel.org; linux-edac@vger.kernel.org;=20 >linux-arm- kernel@lists.infradead.org; james.morse@arm.com;=20 >baicar@os.amperecomputing.com >Cc: zwang@amperecomputing.com; jason@os.amperecomputing.com >Subject: [PATCH v2] arm64/ras: Update code to trace out more data for=20 >ARM processor > >The original arm_event trace code only traces out ARM processor error=20 >information data. According to UEFI_2_8_A_Feb14 specification chapter=20 >N2.4.4, the ARM processor error section includes several ARM processor=20 >error information, several ARM processor context information and=20 >several vendor specific error information structures. > >Add code to trace out all ARM processor context information and vendor=20 >specific error information with raw hex format. > >Signed-off-by: Jason Tian >--- > drivers/ras/ras.c | 22 +++++++++++++++++++++- > include/ras/ras_event.h | 41 +++++++++++++++++++++++++++++++++++--- >--- > 2 files changed, 56 insertions(+), 7 deletions(-) > Tested-by: Shiju Jose >diff --git a/drivers/ras/ras.c b/drivers/ras/ras.c index >95540ea8dd9d..6f3269da9476 100644 >--- a/drivers/ras/ras.c >+++ b/drivers/ras/ras.c >@@ -23,7 +23,27 @@ void log_non_standard_event(const guid_t *sec_type,=20 >const guid_t *fru_id, > > void log_arm_hw_error(struct cper_sec_proc_arm *err) { >- trace_arm_event(err); >+ u32 pei_len; >+ u32 ctx_len; >+ u32 vsei_len; >+ u8 *pei_err; >+ u8 *ctx_err; >+ u8 *ven_err_data; >+ >+ pei_len =3D sizeof(struct cper_arm_err_info) * err->err_info_num; >+ pei_err =3D (u8 *) err + sizeof(struct cper_sec_proc_arm); >+ >+ ctx_len =3D sizeof(struct cper_arm_ctx_info) * err->context_info_num; >+ ctx_err =3D pei_err + sizeof(struct cper_arm_err_info) * >+ err->err_info_num; >+ >+ vsei_len =3D err->section_length - (sizeof(struct cper_sec_proc_arm) + >+ pei_len + ctx_len); >+ ven_err_data =3D ctx_err + sizeof(struct cper_arm_ctx_info) * >+ err->context_info_num; >+ >+ trace_arm_event(err, pei_err, pei_len, ctx_err, ctx_len, >+ ven_err_data, vsei_len); > } > > static int __init ras_init(void) >diff --git a/include/ras/ras_event.h b/include/ras/ras_event.h index >0bdbc0d17d2f..fd9201214be8 100644 >--- a/include/ras/ras_event.h >+++ b/include/ras/ras_event.h >@@ -168,11 +168,22 @@ TRACE_EVENT(mc_event, > * This event is generated when hardware detects an ARM processor=20 >error > * has occurred. UEFI 2.6 spec section N.2.4.4. > */ >+ #define APEIL "ARM Processor Err Info data len" >+ #define APEID "ARM Processor Err Info raw data" >+ #define APECIL "ARM Processor Err Context Info data len" >+ #define APECID "ARM Processor Err Context Info raw data" >+ #define VSEIL "Vendor Specific Err Info data len" >+ #define VSEID "Vendor Specific Err Info raw data" > TRACE_EVENT(arm_event, > >- TP_PROTO(const struct cper_sec_proc_arm *proc), >+ TP_PROTO(const struct cper_sec_proc_arm *proc, const u8 *pei_err, >+ const u32 pei_len, >+ const u8 *ctx_err, >+ const u32 ctx_len, >+ const u8 *oem, >+ const u32 oem_len), > >- TP_ARGS(proc), >+ TP_ARGS(proc, pei_err, pei_len, ctx_err, ctx_len, oem, oem_len), > > TP_STRUCT__entry( > __field(u64, mpidr) >@@ -180,6 +191,12 @@ TRACE_EVENT(arm_event, > __field(u32, running_state) > __field(u32, psci_state) > __field(u8, affinity) >+ __field(u32, pei_len) >+ __dynamic_array(u8, buf, pei_len) >+ __field(u32, ctx_len) >+ __dynamic_array(u8, buf1, ctx_len) >+ __field(u32, oem_len) >+ __dynamic_array(u8, buf2, oem_len) > ), > > TP_fast_assign( >@@ -199,12 +216,24 @@ TRACE_EVENT(arm_event, > __entry->running_state =3D ~0; > __entry->psci_state =3D ~0; > } >+ __entry->pei_len =3D pei_len; >+ memcpy(__get_dynamic_array(buf), pei_err, pei_len); >+ __entry->ctx_len =3D ctx_len; >+ memcpy(__get_dynamic_array(buf1), ctx_err, ctx_len); >+ __entry->oem_len =3D oem_len; >+ memcpy(__get_dynamic_array(buf2), oem, oem_len); > ), > >- TP_printk("affinity level: %d; MPIDR: %016llx; MIDR: %016llx; " >- "running state: %d; PSCI state: %d", >- __entry->affinity, __entry->mpidr, __entry->midr, >- __entry->running_state, __entry->psci_state) >+ TP_printk("affinity level: %d; MPIDR: %016llx; MIDR: %016llx; >running state: %d; " >+ "PSCI state: %d; %s: %d; %s: %s; %s: %d; %s: %s; %s: %d; %s: >%s", >+ __entry->affinity, __entry->mpidr, __entry->midr, >+ __entry->running_state, __entry->psci_state, >+ APEIL, __entry->pei_len, APEID, >+ __print_hex(__get_dynamic_array(buf), __entry->pei_len), >+ APECIL, __entry->ctx_len, APECID, >+ __print_hex(__get_dynamic_array(buf1), __entry->ctx_len), >+ VSEIL, __entry->oem_len, VSEID, >+ __print_hex(__get_dynamic_array(buf2), __entry- >>oem_len)) > ); > > /* >-- >2.25.1 > > >_______________________________________________ >linux-arm-kernel mailing list >linux-arm-kernel@lists.infradead.org >http://lists.infradead.org/mailman/listinfo/linux-arm-kernel Thanks, Shiju