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[23.128.96.18]) by mx.google.com with ESMTP id y11si9291696ede.62.2021.03.09.04.08.45; Tue, 09 Mar 2021 04:09:07 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230462AbhCIMHf (ORCPT + 99 others); Tue, 9 Mar 2021 07:07:35 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:35859 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S230173AbhCIMHU (ORCPT ); Tue, 9 Mar 2021 07:07:20 -0500 X-UUID: a0feffcbd81f44ce95b09b34c67b5c84-20210309 X-UUID: a0feffcbd81f44ce95b09b34c67b5c84-20210309 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1280078577; Tue, 09 Mar 2021 20:07:17 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 9 Mar 2021 20:07:15 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 9 Mar 2021 20:07:15 +0800 From: Macpaul Lin To: Rob Herring , Mark Rutland , Matthias Brugger , Catalin Marinas , Will Deacon , Michael Turquette , Stephen Boyd , Wendell Lin , Fabien Parent , Weiyi Lu , Mars Cheng , Sean Wang , Macpaul Lin , Owen Chen , Evan Green , , Joerg Roedel , Shawn Guo , Marc Zyngier , Ryder Lee , , , , , CC: Ainge Hsu , Eddie Hung , Mediatek WSD Upstream , Macpaul Lin , Macpaul Lin , CC Hwang , Loda Chou Subject: [PATCH v9 4/4] arm64: defconfig: add CONFIG_COMMON_CLK_MT6765_XXX clocks Date: Tue, 9 Mar 2021 20:05:38 +0800 Message-ID: <1615291538-9799-5-git-send-email-macpaul.lin@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1615291538-9799-1-git-send-email-macpaul.lin@mediatek.com> References: <1582279929-11535-1-git-send-email-macpaul.lin@mediatek.com> <1615291538-9799-1-git-send-email-macpaul.lin@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-SNTS-SMTP: FDAF47F11F74DEFFB31581AA99BF3EADAD476DBDEB9F270F6DFD6775057A74402000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Owen Chen Enable MT6765 clock configs, include topckgen, apmixedsys, infracfg, and subsystem clocks. Signed-off-by: Owen Chen Signed-off-by: Macpaul Lin --- arch/arm64/configs/defconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index d612f633b771..553137e81b8e 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -622,6 +622,12 @@ CONFIG_REGULATOR_RK808=y CONFIG_REGULATOR_S2MPS11=y CONFIG_REGULATOR_TPS65132=m CONFIG_REGULATOR_VCTRL=m +CONFIG_COMMON_CLK_MT6765_AUDIOSYS=y +CONFIG_COMMON_CLK_MT6765_CAMSYS=y +CONFIG_COMMON_CLK_MT6765_MMSYS=y +CONFIG_COMMON_CLK_MT6765_IMGSYS=y +CONFIG_COMMON_CLK_MT6765_VCODECSYS=y +CONFIG_COMMON_CLK_MT6765_MIPI0ASYS=y CONFIG_RC_CORE=m CONFIG_RC_DECODERS=y CONFIG_RC_DEVICES=y -- 2.18.0