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From:   Swapnil Kashinath Jakhade <sjakhade@cadence.com>
To:     Kishon Vijay Abraham I <kishon@ti.com>,
        Vinod Koul <vkoul@kernel.org>,
        Rob Herring <robh+dt@kernel.org>, Peter Rosin <peda@axentia.se>
CC:     "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-phy@lists.infradead.org" <linux-phy@lists.infradead.org>
Subject: RE: [PATCH v2 9/9] phy: cadence-torrent: Add support to drive refclk
 out
Thread-Topic: [PATCH v2 9/9] phy: cadence-torrent: Add support to drive refclk
 out
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Date:   Tue, 9 Mar 2021 14:21:46 +0000
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Hi Kishon,

> -----Original Message-----
> From: Kishon Vijay Abraham I <kishon@ti.com>
> Sent: Monday, February 22, 2021 4:53 PM
> To: Kishon Vijay Abraham I <kishon@ti.com>; Vinod Koul
> <vkoul@kernel.org>; Rob Herring <robh+dt@kernel.org>; Peter Rosin
> <peda@axentia.se>; Swapnil Kashinath Jakhade <sjakhade@cadence.com>
> Cc: linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; linux-
> phy@lists.infradead.org
> Subject: [PATCH v2 9/9] phy: cadence-torrent: Add support to drive refclk=
 out
>=20
> EXTERNAL MAIL
>=20
>=20
> cmn_refclk_<p/m> lines in Torrent SERDES is used for connecting external
> reference clock. cmn_refclk_<p/m> can also be configured to output the
> reference clock. Model this derived reference clock as a "clock" so that
> platforms like AM642 EVM can enable it.
>=20
> This is used by PCIe to use the same refclk both in local SERDES
> and remote device. Add support here to drive refclk out.
>=20
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
>  drivers/phy/cadence/phy-cadence-torrent.c | 202 +++++++++++++++++++++-
>  1 file changed, 199 insertions(+), 3 deletions(-)
>=20
> diff --git a/drivers/phy/cadence/phy-cadence-torrent.c
> b/drivers/phy/cadence/phy-cadence-torrent.c
> index f310e15d94cb..07eebdd90d4b 100644
> --- a/drivers/phy/cadence/phy-cadence-torrent.c
> +++ b/drivers/phy/cadence/phy-cadence-torrent.c
> @@ -7,7 +7,9 @@
>   */
>=20
>  #include <dt-bindings/phy/phy.h>
> +#include <dt-bindings/phy/phy-cadence-torrent.h>
>  #include <linux/clk.h>
> +#include <linux/clk-provider.h>
>  #include <linux/delay.h>
>  #include <linux/err.h>
>  #include <linux/io.h>
> @@ -76,6 +78,8 @@
>   * register offsets from SD0801 PHY register block base (i.e MHDP
>   * register base + 0x500000)
>   */
> +#define CMN_CDIAG_REFCLK_OVRD		0x004CU
> +#define CMN_CDIAG_REFCLK_DRV0_CTRL	0x0050U

Nitpick, this can be added sequentially.

>  #define CMN_SSM_BANDGAP_TMR		0x0021U
>  #define CMN_SSM_BIAS_TMR		0x0022U
>  #define CMN_PLLSM0_PLLPRE_TMR		0x002AU
> @@ -206,6 +210,8 @@
>  #define RX_DIAG_ACYA			0x01FFU
>=20
>  /* PHY PCS common registers */
> +#define PHY_PIPE_CMN_CTRL1		0x0000U
> +#define PHY_ISO_CMN_CTRL		0x0008U
>  #define PHY_PLL_CFG			0x000EU
>  #define PHY_PIPE_USB3_GEN2_PRE_CFG0	0x0020U
>  #define PHY_PIPE_USB3_GEN2_POST_CFG0	0x0022U
> @@ -216,6 +222,10 @@
>  #define PHY_PMA_CMN_CTRL2		0x0001U
>  #define PHY_PMA_PLL_RAW_CTRL		0x0003U
>=20
> +static const char * const clk_names[] =3D {
> +	[CDNS_TORRENT_REFCLK_DRIVER] =3D "refclk-driver",
> +};
> +
>  static const struct reg_field phy_pll_cfg =3D
>  				REG_FIELD(PHY_PLL_CFG, 0, 1);
>=20
> @@ -231,6 +241,36 @@ static const struct reg_field phy_pma_pll_raw_ctrl =
=3D
>  static const struct reg_field phy_reset_ctrl =3D
>  				REG_FIELD(PHY_RESET, 8, 8);
>=20
> +#define REFCLK_OUT_NUM_CONFIGURATIONS_PCS_CONFIG	2

This could be reduced just to REFCLK_OUT_NUM_PCS_CONFIG, but up to you.
Same below.

> +
> +enum cdns_torrent_refclk_out_pcs {
> +	PHY_ISO_CMN_CTRL_8,
> +	PHY_PIPE_CMN_CTRL1_0,
> +};
> +
> +#define REFCLK_OUT_NUM_CONFIGURATIONS_CMN_CONFIG	5
> +
> +enum cdns_torrent_refclk_out_cmn {
> +	CMN_CDIAG_REFCLK_OVRD_4,
> +	CMN_CDIAG_REFCLK_DRV0_CTRL_1,
> +	CMN_CDIAG_REFCLK_DRV0_CTRL_4,
> +	CMN_CDIAG_REFCLK_DRV0_CTRL_5,
> +	CMN_CDIAG_REFCLK_DRV0_CTRL_6,
> +};
> +
> +static const struct reg_field refclk_out_pcs_cfg[] =3D {
> +	[PHY_ISO_CMN_CTRL_8]	=3D REG_FIELD(PHY_ISO_CMN_CTRL, 8,
> 8),
> +	[PHY_PIPE_CMN_CTRL1_0]	=3D REG_FIELD(PHY_PIPE_CMN_CTRL1,
> 0, 0),
> +};
> +
> +static const struct reg_field refclk_out_cmn_cfg[] =3D {
> +	[CMN_CDIAG_REFCLK_OVRD_4]	=3D
> REG_FIELD(CMN_CDIAG_REFCLK_OVRD, 4, 4),
> +	[CMN_CDIAG_REFCLK_DRV0_CTRL_1]	=3D
> REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 1, 1),
> +	[CMN_CDIAG_REFCLK_DRV0_CTRL_4]	=3D
> REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 4, 4),
> +	[CMN_CDIAG_REFCLK_DRV0_CTRL_5]  =3D
> REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 5, 5),
> +	[CMN_CDIAG_REFCLK_DRV0_CTRL_6]	=3D
> REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 6, 6),
> +};
> +
>  enum cdns_torrent_phy_type {
>  	TYPE_NONE,
>  	TYPE_DP,
> @@ -279,6 +319,8 @@ struct cdns_torrent_phy {
>  	struct regmap_field *phy_pma_cmn_ctrl_2;
>  	struct regmap_field *phy_pma_pll_raw_ctrl;
>  	struct regmap_field *phy_reset_ctrl;
> +	struct clk *clks[CDNS_TORRENT_REFCLK_DRIVER + 1];
> +	struct clk_onecell_data clk_data;
>  };
>=20
>  enum phy_powerstate {
> @@ -288,6 +330,16 @@ enum phy_powerstate {
>  	POWERSTATE_A3 =3D 3,
>  };
>=20
> +struct cdns_torrent_derived_refclk {
> +	struct clk_hw		hw;
> +	struct regmap_field
> 	*pcs_fields[REFCLK_OUT_NUM_CONFIGURATIONS_PCS_CONFIG];
> +	struct regmap_field
> 	*cmn_fields[REFCLK_OUT_NUM_CONFIGURATIONS_CMN_CONFIG];
> +	struct clk_init_data	clk_data;
> +};
> +
> +#define to_cdns_torrent_derived_refclk(_hw)	\
> +			container_of(_hw, struct
> cdns_torrent_derived_refclk, hw)
> +
>  static int cdns_torrent_phy_init(struct phy *phy);
>  static int cdns_torrent_dp_init(struct phy *phy);
>  static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy,
> @@ -1604,6 +1656,111 @@ static int cdns_torrent_dp_run(struct
> cdns_torrent_phy *cdns_phy, u32 num_lanes)
>  	return ret;
>  }
>=20
> +static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw)
> +{
> +	struct cdns_torrent_derived_refclk *derived_refclk =3D
> to_cdns_torrent_derived_refclk(hw);
> +
> +	regmap_field_write(derived_refclk-
> >cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_6], 0);
> +	regmap_field_write(derived_refclk-
> >cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], 1);
> +	regmap_field_write(derived_refclk-
> >cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_5], 1);
> +	regmap_field_write(derived_refclk-
> >cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 0);
> +	regmap_field_write(derived_refclk-
> >cmn_fields[CMN_CDIAG_REFCLK_OVRD_4], 1);
> +	regmap_field_write(derived_refclk-
> >pcs_fields[PHY_PIPE_CMN_CTRL1_0], 1);
> +	regmap_field_write(derived_refclk-
> >pcs_fields[PHY_ISO_CMN_CTRL_8], 1);
> +
> +	return 0;
> +}
> +
> +static void cdns_torrent_derived_refclk_disable(struct clk_hw *hw)
> +{
> +	struct cdns_torrent_derived_refclk *derived_refclk =3D
> to_cdns_torrent_derived_refclk(hw);
> +
> +	regmap_field_write(derived_refclk-
> >pcs_fields[PHY_ISO_CMN_CTRL_8], 0);
> +}
> +

PHY_ISO_CMN_CTRL is a PHY isolation register. Not sure, but is this correct
to control phy_en_refclk to enable/disable refclk output from here?

> +static int cdns_torrent_derived_refclk_is_enabled(struct clk_hw *hw)
> +{
> +	struct cdns_torrent_derived_refclk *derived_refclk =3D
> to_cdns_torrent_derived_refclk(hw);
> +	int val;
> +
> +	regmap_field_read(derived_refclk-
> >pcs_fields[PHY_ISO_CMN_CTRL_8], &val);
> +
> +	return !!val;
> +}
> +
> +static const struct clk_ops cdns_torrent_derived_refclk_ops =3D {
> +	.enable =3D cdns_torrent_derived_refclk_enable,
> +	.disable =3D cdns_torrent_derived_refclk_disable,
> +	.is_enabled =3D cdns_torrent_derived_refclk_is_enabled,
> +};
> +
> +static int cdns_torrent_derived_refclk_register(struct cdns_torrent_phy
> *cdns_phy)
> +{
> +	struct cdns_torrent_derived_refclk *derived_refclk;
> +	struct device *dev =3D cdns_phy->dev;
> +	struct regmap_field *field;
> +	struct clk_init_data *init;
> +	const char *parent_name;
> +	struct regmap *regmap;
> +	char clk_name[100];
> +	struct clk *clk;
> +	int i;
> +
> +	derived_refclk =3D devm_kzalloc(dev, sizeof(*derived_refclk),
> GFP_KERNEL);
> +	if (!derived_refclk)
> +		return -ENOMEM;
> +
> +	snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
> +		 clk_names[CDNS_TORRENT_REFCLK_DRIVER]);
> +
> +	clk =3D devm_clk_get_optional(dev, "phy_en_refclk");
> +	if (IS_ERR(clk)) {
> +		dev_err(dev, "No parent clock for derived_refclk\n");
> +		return PTR_ERR(clk);
> +	}
> +
> +	init =3D &derived_refclk->clk_data;
> +
> +	if (clk) {
> +		parent_name =3D __clk_get_name(clk);
> +		init->parent_names =3D &parent_name;
> +		init->num_parents =3D 1;
> +	}
> +	init->ops =3D &cdns_torrent_derived_refclk_ops;
> +	init->flags =3D 0;
> +	init->name =3D clk_name;
> +
> +	regmap =3D cdns_phy->regmap_phy_pcs_common_cdb;
> +	for (i =3D 0; i < REFCLK_OUT_NUM_CONFIGURATIONS_PCS_CONFIG;
> i++) {
> +		field =3D devm_regmap_field_alloc(dev, regmap,
> refclk_out_pcs_cfg[i]);
> +		if (IS_ERR(field)) {
> +			dev_err(dev, "PCS reg field init failed\n");
> +			return PTR_ERR(field);
> +		}
> +		derived_refclk->pcs_fields[i] =3D field;
> +	}
> +
> +	regmap =3D cdns_phy->regmap_common_cdb;
> +	for (i =3D 0; i < REFCLK_OUT_NUM_CONFIGURATIONS_CMN_CONFIG;
> i++) {
> +		field =3D devm_regmap_field_alloc(dev, regmap,
> refclk_out_cmn_cfg[i]);
> +		if (IS_ERR(field)) {
> +			dev_err(dev, "CMN reg field init failed\n");
> +			return PTR_ERR(field);
> +		}
> +		derived_refclk->cmn_fields[i] =3D field;
> +	}
> +
> +	derived_refclk->hw.init =3D init;
> +
> +	clk =3D devm_clk_register(dev, &derived_refclk->hw);
> +	if (IS_ERR(clk))
> +		return PTR_ERR(clk);
> +
> +	cdns_phy->clks[CDNS_TORRENT_REFCLK_DRIVER] =3D clk;
> +
> +	return 0;
> +}
> +
>  static int cdns_torrent_phy_on(struct phy *phy)
>  {
>  	struct cdns_torrent_inst *inst =3D phy_get_drvdata(phy);
> @@ -2071,6 +2228,37 @@ int cdns_torrent_phy_configure_multilink(struct
> cdns_torrent_phy *cdns_phy)
>  	return 0;
>  }
>=20
> +static void cdns_torrent_clk_cleanup(struct cdns_torrent_phy *cdns_phy)
> +{
> +	struct device *dev =3D cdns_phy->dev;
> +
> +	of_clk_del_provider(dev->of_node);
> +}
> +
> +static int cdns_torrent_clk_register(struct cdns_torrent_phy *cdns_phy)
> +{
> +	struct device *dev =3D cdns_phy->dev;
> +	struct device_node *node =3D dev->of_node;
> +	int ret;
> +
> +	ret =3D cdns_torrent_derived_refclk_register(cdns_phy);
> +	if (ret) {
> +		dev_err(dev, "failed to register derived refclk\n");
> +		return ret;
> +	}
> +
> +	cdns_phy->clk_data.clks =3D cdns_phy->clks;
> +	cdns_phy->clk_data.clk_num =3D CDNS_TORRENT_REFCLK_DRIVER + 1;
> +
> +	ret =3D of_clk_add_provider(node, of_clk_src_onecell_get, &cdns_phy-
> >clk_data);
> +	if (ret) {
> +		dev_err(dev, "Failed to add clock provider: %s\n", node-
> >name);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
>  static int cdns_torrent_phy_probe(struct platform_device *pdev)
>  {
>  	struct cdns_torrent_phy *cdns_phy;
> @@ -2134,17 +2322,21 @@ static int cdns_torrent_phy_probe(struct
> platform_device *pdev)
>  	if (ret)
>  		return ret;
>=20
> +	ret =3D cdns_torrent_clk_register(cdns_phy);
> +	if (ret)
> +		return ret;
> +
>  	ret =3D clk_prepare_enable(cdns_phy->clk);
>  	if (ret) {
>  		dev_err(cdns_phy->dev, "Failed to prepare ref clock\n");
> -		return ret;
> +		goto clk_cleanup;
>  	}
>=20
>  	cdns_phy->ref_clk_rate =3D clk_get_rate(cdns_phy->clk);
>  	if (!(cdns_phy->ref_clk_rate)) {
>  		dev_err(cdns_phy->dev, "Failed to get ref clock rate\n");
> -		clk_disable_unprepare(cdns_phy->clk);
> -		return -EINVAL;
> +		ret =3D -EINVAL;
> +		goto clk_disable;
>  	}
>=20
>  	/* Enable APB */
> @@ -2322,7 +2514,10 @@ static int cdns_torrent_phy_probe(struct
> platform_device *pdev)
>  		reset_control_put(cdns_phy->phys[i].lnk_rst);
>  	of_node_put(child);
>  	reset_control_assert(cdns_phy->apb_rst);
> +clk_disable:
>  	clk_disable_unprepare(cdns_phy->clk);
> +clk_cleanup:
> +	cdns_torrent_clk_cleanup(cdns_phy);
>  	return ret;
>  }
>=20
> @@ -2339,6 +2534,7 @@ static int cdns_torrent_phy_remove(struct
> platform_device *pdev)
>  	}
>=20
>  	clk_disable_unprepare(cdns_phy->clk);
> +	cdns_torrent_clk_cleanup(cdns_phy);
>=20
>  	return 0;
>  }
> --
> 2.17.1

Thanks & regards,
Swapnil