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[23.128.96.18]) by mx.google.com with ESMTP id q17si13236782edb.68.2021.03.10.02.45.26; Wed, 10 Mar 2021 02:45:48 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232033AbhCJKob (ORCPT + 99 others); Wed, 10 Mar 2021 05:44:31 -0500 Received: from foss.arm.com ([217.140.110.172]:43610 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232459AbhCJKo3 (ORCPT ); Wed, 10 Mar 2021 05:44:29 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 350F81FB; Wed, 10 Mar 2021 02:44:29 -0800 (PST) Received: from C02TD0UTHF1T.local (unknown [10.57.52.108]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 272EA3F85F; Wed, 10 Mar 2021 02:44:27 -0800 (PST) Date: Wed, 10 Mar 2021 10:44:21 +0000 From: Mark Rutland To: Rob Herring , Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Alexandru Elisei , Julien Thierry , Catalin Marinas , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin , Jiri Olsa , Namhyung Kim Subject: Re: [PATCH] arm64: perf: Fix 64-bit event counter read truncation Message-ID: <20210310104348.GA19001@C02TD0UTHF1T.local> References: <20210310004412.1450128-1-robh@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210310004412.1450128-1-robh@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Mar 09, 2021 at 05:44:12PM -0700, Rob Herring wrote: > Commit 0fdf1bb75953 ("arm64: perf: Avoid PMXEV* indirection") changed > armv8pmu_read_evcntr() to return a u32 instead of u64. The result is > silent truncation of the event counter when using 64-bit counters. Given > the offending commit appears to have passed thru several folks, it seems > likely this was a bad rebase after v8.5 PMU 64-bit counters landed. IIRC I wrote the indirection patch first, so this does sound like an oversight when rebasing or reworking the patch. Comparing against commit 0fdf1bb75953, this does appear to be the only point of truncation given read_pmevcntrn() directly returns the result of read_sysreg(), so: Acked-by: Mark Rutland Will, could you pick this up? Thanks, Mark. > Fixes: 0fdf1bb75953 ("arm64: perf: Avoid PMXEV* indirection") > Cc: Alexandru Elisei > Cc: Julien Thierry > Cc: Mark Rutland > Cc: Will Deacon > Cc: Catalin Marinas > Cc: Peter Zijlstra > Cc: Ingo Molnar > Cc: Arnaldo Carvalho de Melo > Cc: Alexander Shishkin > Cc: Jiri Olsa > Cc: Namhyung Kim > Signed-off-by: Rob Herring > --- > arch/arm64/kernel/perf_event.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c > index 7d2318f80955..4658fcf88c2b 100644 > --- a/arch/arm64/kernel/perf_event.c > +++ b/arch/arm64/kernel/perf_event.c > @@ -460,7 +460,7 @@ static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx) > return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx)); > } > > -static inline u32 armv8pmu_read_evcntr(int idx) > +static inline u64 armv8pmu_read_evcntr(int idx) > { > u32 counter = ARMV8_IDX_TO_COUNTER(idx); > > -- > 2.27.0 >