Received: by 2002:a05:6a10:9848:0:0:0:0 with SMTP id x8csp615464pxf; Wed, 10 Mar 2021 13:16:00 -0800 (PST) X-Google-Smtp-Source: ABdhPJziDCdImdi8oYAHNrvva6J85vkbln8WqMkTmgUb3qHuRJ/ngj1hzTcOoTzqRfbN2Q13wCZQ X-Received: by 2002:a05:6402:138f:: with SMTP id b15mr4688257edv.121.1615410960082; Wed, 10 Mar 2021 13:16:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615410960; cv=none; d=google.com; s=arc-20160816; b=0ZHR9PQh8v55jN4/5RRbqc9m2MiqU67+wEsrrLYfhgfybktzJha7JIxk0cz68Gsxri oKAfWEhcPFR2iya7KLE3GgbHKoeOd+fx7AIIuOR3R8tbQj/vIybeqfH+ZoJjV4FJpgR8 Sq4cqOp7rODuSIyY43jCuJFJTt25MnCzqLTB/XWX2AVajYeFr4DgZPSyEqMY1UlSM09d 8r0YI9xxhXdbYgqYaokjzZ6alTIUTdoufy7gsaniUja5KxEtEi+N9x1VBeVrY6tzl5Or O7pTMGzp7I/Jwr0MZtkCMRxFcLRSWJWrC37pgAxtU/frU3ZZvLbxsvT6wOj2p8pTZqBu ulzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=4FsyvPll9hketVRRLkgN32e9nK5xbA0yUQ+/xWtjN5A=; b=FslEEqxb7m7TUZOD4mjmJjXHfX1aojqmg2hjug2G+Bmi0xOqs3hf2JvwWd4b6L80gp 5CeXxYKfzRE3+iUiM7MwbFbUAfiwq0AcW3yTF77jzwqul28dI3gDhxhqjQaTJZhguabB P73pLWZU0fdzaVktXAEORAN6iX0rqWQJcKzfgiRp1hO/UDBoXzKx8oHq3wSXY8tJldqP JlVUk0vrMfUxrMKqMBbV4zBiKJP9kXS3kP5He6AxCY3lG1v0a8E28sMpzjxKGu1AvBZj AC2fDMUxiOxu4YLDTdJLUFJ1ZNxxKyWUZS0Ao1EQp8Rr46EQuemSCj+Xlo1wdYeFvrjj AgWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=sS6imgOp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id o2si336514ejx.336.2021.03.10.13.15.37; Wed, 10 Mar 2021 13:16:00 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=sS6imgOp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231984AbhCJVOk (ORCPT + 99 others); Wed, 10 Mar 2021 16:14:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34784 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231935AbhCJVOZ (ORCPT ); Wed, 10 Mar 2021 16:14:25 -0500 Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 80D3BC061574; Wed, 10 Mar 2021 13:14:25 -0800 (PST) Received: by mail-pj1-x1036.google.com with SMTP id x7-20020a17090a2b07b02900c0ea793940so7946927pjc.2; Wed, 10 Mar 2021 13:14:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=4FsyvPll9hketVRRLkgN32e9nK5xbA0yUQ+/xWtjN5A=; b=sS6imgOph8gR00hEK59z03oQEPnKC5OOit9DuHc9a9zW2bnRVXnbj4Sw2fC032b0w1 Z40vFIAbd7Yg2JVUAlD0lsjjiKM5UyAS4EBh/3RAhonPZdbdzZcrXYiidJo2DkgJX2nL iiny/jjkthqyHfBbwuEkA44ykbHmGoMM97WzSzveom1U4u9koOGpnryhADOT/I6WTQ3u IH6mSU5vuAWSxYl6cCvbPWu2QDBsWEaMnM1KP2S0K5uk6gp0ZG/JBh1LXBnnibnqDEA2 6H7ZYyd/lbb+asSbJAIYAIMIALiWGYV8PnZXdwrX/iXVy5Khvx/t581cLa1Preoz7UaU M6+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=4FsyvPll9hketVRRLkgN32e9nK5xbA0yUQ+/xWtjN5A=; b=Q8hD+T2j5+sDwgZHGhtZilFVJe1oQVjPf5SDVw/6eafdq3MUgLxZibktyZOJt7QAxN iy2MDlcLH2jpErQWygkGEzAlKfWnqRVuVPYdRCgTL60eFtDspvXXKY/YszvJ/hUXrmyv xOIZusAAiMMvZK+5CUxCNvGFM35q9kOl7Qtq2rpCflfO7SgP8adcD78Wq5d3ZtuyJU1o KrhzW/stVu96b6zvXXgJ8VXyfctRWrqHknK1hCsM28ckHrZfduiTbnmGxAPi40jKvDXx 0ANqvNLvJvYc0GV1QtWlJTZxrsY5fgdgmBvGU2XPqSg1tMiLh0lVuHsSOmIz8jdeH1Y4 rTQg== X-Gm-Message-State: AOAM5327lkZR4N+Tm9xyberjq/Qz2Bf+Y9FcTJg9IGxyoG4AQHlbJt5S 4Ozw4Y64gdJOrnRR23wN14s= X-Received: by 2002:a17:90b:3890:: with SMTP id mu16mr5447946pjb.9.1615410865096; Wed, 10 Mar 2021 13:14:25 -0800 (PST) Received: from ilya-fury.lan ([2602:61:738f:1000::b87]) by smtp.gmail.com with ESMTPSA id 35sm412090pgr.14.2021.03.10.13.14.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Mar 2021 13:14:24 -0800 (PST) From: Ilya Lipnitskiy To: Sean Wang , Landen Chao , Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Matthias Brugger , Philipp Zabel , Russell King , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Ilya Lipnitskiy Subject: [PATCH 1/3] net: dsa: mt7530: remove redundant clock enables Date: Wed, 10 Mar 2021 13:14:18 -0800 Message-Id: <20210310211420.649985-1-ilya.lipnitskiy@gmail.com> X-Mailer: git-send-email 2.30.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In RGMII mode, the REG_GSWCK_EN bit of CORE_TRGMII_GSW_CLK_CG gets set three times in a row. In TRGMII mode, two times. Simplify the code and only set it once for both modes. Signed-off-by: Ilya Lipnitskiy --- drivers/net/dsa/mt7530.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index f06f5fa2f898..e785f80f966b 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -461,12 +461,9 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) RG_GSWPLL_POSDIV_200M(2) | RG_GSWPLL_FBKDIV_200M(32)); - /* Enable MT7530 core clock */ - core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); } /* Setup the MT7530 TRGMII Tx Clock */ - core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); @@ -480,6 +477,8 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) core_write(priv, CORE_PLL_GROUP7, RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); + + /* Enable MT7530 core and TRGMII Tx clocks */ core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN | REG_TRGMIICK_EN); -- 2.30.1