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[23.128.96.18]) by mx.google.com with ESMTP id t8si1659897ejj.661.2021.03.11.04.35.18; Thu, 11 Mar 2021 04:35:40 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@0x0f.com header.s=google header.b="q1H/SxQD"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233214AbhCKMcl (ORCPT + 99 others); Thu, 11 Mar 2021 07:32:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233266AbhCKMcM (ORCPT ); Thu, 11 Mar 2021 07:32:12 -0500 Received: from mail-qk1-x734.google.com (mail-qk1-x734.google.com [IPv6:2607:f8b0:4864:20::734]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7DD9DC061574 for ; Thu, 11 Mar 2021 04:32:12 -0800 (PST) Received: by mail-qk1-x734.google.com with SMTP id n79so20342811qke.3 for ; Thu, 11 Mar 2021 04:32:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=E7/MPGIZ4WfmL4CRUvFWlovc/8lRT5Q/WOgdo9DvGsk=; b=q1H/SxQD3WDk3KLYZMwT6Gf63+upJzj5dCh1F/YNzNXw5uyBTozuGVXrxupcAsUfIz 7j+gAgISYDyG2F5C7PkLQszFIFP9Mg1Pk84HaCQLRkMKJyxa2LY1Rn5Lpp6aLd0aEyw0 pBr8pscVWyZww9IlPVkBnPHRacGB6Zu17GRrU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=E7/MPGIZ4WfmL4CRUvFWlovc/8lRT5Q/WOgdo9DvGsk=; b=lqMAkCES+t/yEN0UPVfoRUAD1x1eyEyN7dq29a2BV1Etnwwzs5S8OlXnbXJYLxAPQu y+8nk6sO2CKtF5A+aDwy3cNOIBDJLDrGEsatEiqj36OrchtyXZeXlNXlO7YKHtcGAOTo JxlLClfvrOgQMf7NGRrWdiOYgz3YMklE4N14lnSIbtcQGMSsDqVSkCiRWytQr4tKrE8V mjEfe93vrTRJmoD+J0VMz/mw3LGpvgIbDGarxEDKMiI1OeSp5bDu58QFRfmyi9SeuDcX 1zjbaZHkOVQ5DeRMLby1CtGetij2I8U73p3Pror7pyeAEID3/p8xsQBvqhaMlty8XJ4D PWwA== X-Gm-Message-State: AOAM532ylmoVEG0PQ99mBAUUOjcf6ywk6BAMsA8SBGqSK5wgV2+zSTK5 iv0Fff2yDKvhmBPXI5AZAfWZ9N2WTQ524KP/fIffMg== X-Received: by 2002:a37:ef09:: with SMTP id j9mr7386300qkk.390.1615465931646; Thu, 11 Mar 2021 04:32:11 -0800 (PST) MIME-Version: 1.0 References: <20210311031242.24232-1-mark-pk.tsai@mediatek.com> In-Reply-To: <20210311031242.24232-1-mark-pk.tsai@mediatek.com> From: Daniel Palmer Date: Thu, 11 Mar 2021 21:33:35 +0900 Message-ID: Subject: Re: [PATCH v2] irqchip/irq-mst: Support polarity configuration To: Mark-PK Tsai Cc: Daniel Palmer , linux-arm-kernel , Linux Kernel Mailing List , linux-mediatek@lists.infradead.org, Matthias Brugger , Marc Zyngier , Thomas Gleixner , =?UTF-8?B?WUogQ2hpYW5nICjmsZ/oi7HmnbAp?= Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Mark-PK. On Thu, 11 Mar 2021 at 12:12, Mark-PK Tsai wrote: > For a fiq controller, the input edge signal will be convert to level and > keep the interrupt status until we do EOI operation. > That means if a rising edge input if trigger the ouput line will keep high > until we clear the interrupt status. I think maybe the fiq is always edge triggered? It seems like it latches on an edge and holds it's output to the GIC high until it is reset by eoi and then only triggers again on another edge. I can experiment to confirm that's what it actually does for the chips I have. Then it seems like the irq version is almost just a configurable inverter that passes either the input signal or the inverted input signal to the GIC. So maybe fiq should only accept edge type interrupts and irq could accept either? > static int mst_irq_chip_set_type(struct irq_data *data, unsigned int type) > { > - if (type != IRQ_TYPE_LEVEL_LOW && type != IRQ_TYPE_LEVEL_HIGH) > - return -EINVAL; > - > - if (type == IRQ_TYPE_LEVEL_LOW) { > + if (type == IRQ_TYPE_EDGE_FALLING) { > + mst_set_irq(data, INTC_REV_POLARITY); > + type = IRQ_TYPE_EDGE_RISING; > + } else if (type == IRQ_TYPE_LEVEL_LOW) { > mst_set_irq(data, INTC_REV_POLARITY); > type = IRQ_TYPE_LEVEL_HIGH; > } I think this still needs the logic to check that type is something we can handle (not IRQ_TYPE_EDGE_BOTH) and maybe if the fiq controller can only do edge interrupts level types should return -EINVAL? Thanks, Daniel