Received: by 2002:a05:6a10:9848:0:0:0:0 with SMTP id x8csp891163pxf; Thu, 11 Mar 2021 18:28:40 -0800 (PST) X-Google-Smtp-Source: ABdhPJx16UUsYRvZ52diBD7yEHlsUcD9ZTOUh0bhXF45s2CZ6YPGxd2eSaERzydt7nbVQ58CYApc X-Received: by 2002:aa7:dc04:: with SMTP id b4mr11496194edu.221.1615516119961; Thu, 11 Mar 2021 18:28:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615516119; cv=none; d=google.com; s=arc-20160816; b=b0upzcWBWzFai/0nsc9RNZDswwEzJzaSLL4VxWt5E1oNeHwaCP+mF7XwE7qckt9GzC p+qhuij8lAmcbPmai/9x+77JA4gy51kd/9+iyssAxTgFVi91ejBwv8Uov69Cp3gu1tF8 K3C9uIMtAc9itUahXpglL+a4nQfwiNg082rkXquhnNbPqHD/B2XN44vHjO4SnO//c7lC xzIvZ+1AEL8M7hQxVPcXiKdVF4puWpCa/NPgBRAGDlO8juoTMATMtG11tblUqWKKM7m6 l6kPbtF1bQqJC35t5Chze+zQC/JTe0PqeCzWpSmrtR/Pi6K4hQ/faugrTCIktR72u5MX pgiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:message-id:date:subject:cc:to:from; bh=3CQmQt80vBoKRehrt/GjWqbfZJyPCJ5GCqu+XC6MB4c=; b=b/K1THrjQQTKrSvK++jY40EZ6tZ/MSCc0o6ZUspSTv4AwDaFXnwIRPkd/wBlt2xocr hAeWw5jqt5UBsP5KGlO3FaZJfykRovDzY+Jrrn2OguGyiKA92uCFEJXRcyzCSOsYHfLr m8lgBkpiSCLkvLNhe18nXzNYIBe+9jHQ/+PM2clD5z+Uu4rTMbhBpMa5gBU+zEpOk/Dj vbmkBCukoFfmHutOFaJaqpiDXLThmWucdaT2X0dFdHIVoXeCn/1Ws257vgwZAD7VcgRo vrLljjCR/t/GQdMJvP4m8s11w1b9FGht/lF23hhWNVun+cgEv0U75XlPCROgb+jjs0jL EXFg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id o14si3125871edz.435.2021.03.11.18.28.16; Thu, 11 Mar 2021 18:28:39 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231197AbhCLC1H (ORCPT + 99 others); Thu, 11 Mar 2021 21:27:07 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:49742 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229737AbhCLC0v (ORCPT ); Thu, 11 Mar 2021 21:26:51 -0500 X-UUID: 3b2e1080fb164915960c585295b6b8a1-20210312 X-UUID: 3b2e1080fb164915960c585295b6b8a1-20210312 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 921633192; Fri, 12 Mar 2021 10:26:49 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 12 Mar 2021 10:26:48 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 12 Mar 2021 10:26:47 +0800 From: Jiaxin Yu To: , , , , , , CC: , , Jiaxin Yu Subject: [PATCH] ASoC: mediatek: mt8192: fix tdm out data is valid on rising edge Date: Fri, 12 Mar 2021 10:26:45 +0800 Message-ID: <1615516005-781-1-git-send-email-jiaxin.yu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch correct tdm out bck inverse register to AUDIO_TOP_CON3[3]. Signed-off-by: Jiaxin Yu --- sound/soc/mediatek/mt8192/mt8192-dai-tdm.c | 4 +++- sound/soc/mediatek/mt8192/mt8192-reg.h | 8 +++++--- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/sound/soc/mediatek/mt8192/mt8192-dai-tdm.c b/sound/soc/mediatek/mt8192/mt8192-dai-tdm.c index f5de1d769679..f3bebed2428a 100644 --- a/sound/soc/mediatek/mt8192/mt8192-dai-tdm.c +++ b/sound/soc/mediatek/mt8192/mt8192-dai-tdm.c @@ -555,7 +555,9 @@ static int mtk_dai_tdm_hw_params(struct snd_pcm_substream *substream, /* set tdm */ if (tdm_priv->bck_invert) - tdm_con |= 1 << BCK_INVERSE_SFT; + regmap_update_bits(afe->regmap, AUDIO_TOP_CON3, + BCK_INVERSE_MASK_SFT, + 0x1 << BCK_INVERSE_SFT); if (tdm_priv->lck_invert) tdm_con |= 1 << LRCK_INVERSE_SFT; diff --git a/sound/soc/mediatek/mt8192/mt8192-reg.h b/sound/soc/mediatek/mt8192/mt8192-reg.h index 562f25c79c34..b9fb80d4afec 100644 --- a/sound/soc/mediatek/mt8192/mt8192-reg.h +++ b/sound/soc/mediatek/mt8192/mt8192-reg.h @@ -21,6 +21,11 @@ enum { /***************************************************************************** * R E G I S T E R D E F I N I T I O N *****************************************************************************/ +/* AUDIO_TOP_CON3 */ +#define BCK_INVERSE_SFT 3 +#define BCK_INVERSE_MASK 0x1 +#define BCK_INVERSE_MASK_SFT (0x1 << 3) + /* AFE_DAC_CON0 */ #define VUL12_ON_SFT 31 #define VUL12_ON_MASK 0x1 @@ -2079,9 +2084,6 @@ enum { #define TDM_EN_SFT 0 #define TDM_EN_MASK 0x1 #define TDM_EN_MASK_SFT (0x1 << 0) -#define BCK_INVERSE_SFT 1 -#define BCK_INVERSE_MASK 0x1 -#define BCK_INVERSE_MASK_SFT (0x1 << 1) #define LRCK_INVERSE_SFT 2 #define LRCK_INVERSE_MASK 0x1 #define LRCK_INVERSE_MASK_SFT (0x1 << 2) -- 2.18.0