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[23.128.96.18]) by mx.google.com with ESMTP id dj20si3888992edb.250.2021.03.12.02.31.22; Fri, 12 Mar 2021 02:31:45 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@eaxlabs.cz header.s=mail header.b=LhXTPXw0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233280AbhCLK3t (ORCPT + 99 others); Fri, 12 Mar 2021 05:29:49 -0500 Received: from smtp.wifcom.cz ([85.207.3.150]:51725 "EHLO smtp.wifcom.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231929AbhCLK3p (ORCPT ); Fri, 12 Mar 2021 05:29:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=eaxlabs.cz; s=mail; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=kSXHXTR/TeMt8/zrDo1WiK6sqLAP5dPJKbJ+mSkPfN4=; b=LhXTPXw0awQSrl8BO5N8y1J/1Zvxc/HeVmmLkA/WuJn/dSgiF6hKEOn+JzyOmX2rn4Q2wASaQlplmReEL3rteGKKHInwO87jgrZj6g/c614/gXoxJIOMlJ9nXGoDMHc5psXqa2wLBIvsDpA9WxFUUlHgtt0Tevb55nFZgzo3Lgs=; From: Martin Devera To: linux-kernel@vger.kernel.org Cc: Martin Devera , Greg Kroah-Hartman , Rob Herring , Maxime Coquelin , Alexandre Torgue , Jiri Slaby , Le Ray , fabrice.gasnier@foss.st.com, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH v6 2/2] tty/serial: Add rx-tx-swap OF option to stm32-usart Date: Fri, 12 Mar 2021 11:27:13 +0100 Message-Id: <20210312102713.27776-2-devik@eaxlabs.cz> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20210312102713.27776-1-devik@eaxlabs.cz> References: <20210312102713.27776-1-devik@eaxlabs.cz> X-Antivirus-Scanner: Clean mail though you should still use an Antivirus X-Wif-ss: -2.9 (--) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org STM32 F7/H7 usarts supports RX & TX pin swapping. Add option to turn it on. Tested on STM32MP157. Signed-off-by: Martin Devera Acked-by: Fabrice Gasnier --- v6: - add version changelog v4: - delete superfluous has_swap=false v3: - add has_swap to stm32_usart_info (because F4 line doesn't support swapping) - move swap variable init from stm32_usart_of_get_port to stm32_usart_init_port because info struct is not initialized in stm32_usart_of_get_port yet - set USART_CR2_SWAP in stm32_usart_startup too v2: - change st,swap to rx-tx-swap (pointed out by Rob Herring) - rebase patches as suggested by Greg Kroah-Hartman --- drivers/tty/serial/stm32-usart.c | 11 ++++++++++- drivers/tty/serial/stm32-usart.h | 4 ++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c index b3675cf25a69..d390f7da1441 100644 --- a/drivers/tty/serial/stm32-usart.c +++ b/drivers/tty/serial/stm32-usart.c @@ -644,6 +644,12 @@ static int stm32_usart_startup(struct uart_port *port) if (ret) return ret; + if (stm32_port->swap) { + val = readl_relaxed(port->membase + ofs->cr2); + val |= USART_CR2_SWAP; + writel_relaxed(val, port->membase + ofs->cr2); + } + /* RX FIFO Flush */ if (ofs->rqr != UNDEF_REG) stm32_usart_set_bits(port, ofs->rqr, USART_RQR_RXFRQ); @@ -758,7 +764,7 @@ static void stm32_usart_set_termios(struct uart_port *port, cr1 = USART_CR1_TE | USART_CR1_RE; if (stm32_port->fifoen) cr1 |= USART_CR1_FIFOEN; - cr2 = 0; + cr2 = stm32_port->swap ? USART_CR2_SWAP : 0; cr3 = readl_relaxed(port->membase + ofs->cr3); cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG_MASK | USART_CR3_RXFTIE | USART_CR3_TXFTCFG_MASK; @@ -1006,6 +1012,9 @@ static int stm32_usart_init_port(struct stm32_port *stm32port, return stm32port->wakeirq ? : -ENODEV; } + stm32port->swap = stm32port->info->cfg.has_swap && + of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"); + stm32port->fifoen = stm32port->info->cfg.has_fifo; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); diff --git a/drivers/tty/serial/stm32-usart.h b/drivers/tty/serial/stm32-usart.h index cb4f327c46db..a85391e71e8e 100644 --- a/drivers/tty/serial/stm32-usart.h +++ b/drivers/tty/serial/stm32-usart.h @@ -25,6 +25,7 @@ struct stm32_usart_offsets { struct stm32_usart_config { u8 uart_enable_bit; /* USART_CR1_UE */ bool has_7bits_data; + bool has_swap; bool has_wakeup; bool has_fifo; int fifosize; @@ -76,6 +77,7 @@ struct stm32_usart_info stm32f7_info = { .cfg = { .uart_enable_bit = 0, .has_7bits_data = true, + .has_swap = true, .fifosize = 1, } }; @@ -97,6 +99,7 @@ struct stm32_usart_info stm32h7_info = { .cfg = { .uart_enable_bit = 0, .has_7bits_data = true, + .has_swap = true, .has_wakeup = true, .has_fifo = true, .fifosize = 16, @@ -271,6 +274,7 @@ struct stm32_port { int last_res; bool tx_dma_busy; /* dma tx busy */ bool hw_flow_control; + bool swap; /* swap RX & TX pins */ bool fifoen; int wakeirq; int rdr_mask; /* receive data register mask */ -- 2.11.0