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Fri, 12 Mar 2021 12:57:26 +0000 Subject: Re: [PATCH RFC v1 08/15] iommu: Add asid_bits to arm smmu-v3 stage1 table info To: Jean-Philippe Brucker Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, virtualization@lists.linux-foundation.org, joro@8bytes.org, will.deacon@arm.com, mst@redhat.com, robin.murphy@arm.com, eric.auger@redhat.com, alex.williamson@redhat.com, kevin.tian@intel.com, jacob.jun.pan@linux.intel.com, yi.l.liu@intel.com, lorenzo.pieralisi@arm.com, shameerali.kolothum.thodi@huawei.com References: <20210115121342.15093-1-vivek.gautam@arm.com> <20210115121342.15093-9-vivek.gautam@arm.com> From: Vivek Kumar Gautam Message-ID: Date: Fri, 12 Mar 2021 18:27:18 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [217.140.105.56] X-ClientProxiedBy: BMXPR01CA0001.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:d::11) To AM0PR08MB3268.eurprd08.prod.outlook.com (2603:10a6:208:65::26) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from [10.162.16.71] (217.140.105.56) by BMXPR01CA0001.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:d::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3912.17 via Frontend Transport; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2021 12:57:39.9360 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d6045380-0594-4a9e-1766-08d8e5566b22 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT054.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB6441 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 3/3/21 10:48 PM, Jean-Philippe Brucker wrote: > On Fri, Jan 15, 2021 at 05:43:35PM +0530, Vivek Gautam wrote: >> aisd_bits data is required to prepare stage-1 tables for arm-smmu-v3. >> >> Signed-off-by: Vivek Gautam >> Cc: Joerg Roedel >> Cc: Will Deacon >> Cc: Robin Murphy >> Cc: Jean-Philippe Brucker >> Cc: Eric Auger >> Cc: Alex Williamson >> Cc: Kevin Tian >> Cc: Jacob Pan >> Cc: Liu Yi L >> Cc: Lorenzo Pieralisi >> Cc: Shameerali Kolothum Thodi >> --- >> include/uapi/linux/iommu.h | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/include/uapi/linux/iommu.h b/include/uapi/linux/iommu.h >> index 082d758dd016..96abbfc7c643 100644 >> --- a/include/uapi/linux/iommu.h >> +++ b/include/uapi/linux/iommu.h >> @@ -357,7 +357,7 @@ struct iommu_pasid_smmuv3 { >> __u32 version; >> __u8 s1fmt; >> __u8 s1dss; >> - __u8 padding[2]; >> + __u16 asid_bits; > > Is this used anywhere? This struct is passed from host userspace to host > kernel to attach the PASID table, so I don't think it needs an asid_bits > field. Yea, must have missed removing it from the WIP work. Will remove it. Thanks Vivek