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[23.128.96.18]) by mx.google.com with ESMTP id t6si6633343edw.202.2021.03.13.07.20.09; Sat, 13 Mar 2021 07:20:32 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@telus.net header.s=google header.b=FwQcHCgA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=telus.net Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233945AbhCMPRC (ORCPT + 99 others); Sat, 13 Mar 2021 10:17:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39482 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233923AbhCMPQk (ORCPT ); Sat, 13 Mar 2021 10:16:40 -0500 Received: from mail-il1-x12e.google.com (mail-il1-x12e.google.com [IPv6:2607:f8b0:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE03AC061762 for ; Sat, 13 Mar 2021 07:16:39 -0800 (PST) Received: by mail-il1-x12e.google.com with SMTP id d5so5372605iln.6 for ; Sat, 13 Mar 2021 07:16:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=telus.net; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Bx9YKE7djfRDbvG/EReeeOxeC1xP/y2DgKagfSaju7s=; b=FwQcHCgALVnUwbkiKx+5VCM+o2rXXCEEdf5EUyA3NlNNXHHVYgH6g+M7ZfKPDwuzrP AFiorwohVqP1K6/SVA+ccbDVWlTzXbRxphjwHi93ZgtiOQgnvwQ++3eNrqiWPIfIYjux EVb0CiDweiFQ/KN12Xm9kAQiUQXU5sLx9q5R1NkL6ogyAtxITaQJ0UYQt+/HznE4GT/t FUuCHOtpcVxQMlhR5KzGGbBC5LcJuu/2xPbdYBLAqwi695YfIUSuLZ1CRW9P7xzA6RjU G6HUbBYGTnrCRaEsYhHuh4OjLXWrH+V50BtrQC8QHtdISPxvmrgL0+JsNnBE9Ui0vvjm WQFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Bx9YKE7djfRDbvG/EReeeOxeC1xP/y2DgKagfSaju7s=; b=qNWK4oxOx604Nj63fYRwfw+bxO7qOJvxbP918JFzRFmQhl/2C6VNH8oBIXPSwlob63 jzRXBiPi7r8eOSsEZpwXPycX5ZpxDdc7i3e71Yjp5jo5N3qzU8psIFxsAHKOnyQvwB3G WWFzoiSFlpXAsopKT/rXleg/Kwg+V1gdVFikGnTc8cvF12jNTOl0uloTScyPwjM5yZ+v 52K6uHdfHuCJnFf6JetaLR/CE/A31/X2K36/6QxmPI6VYl0u1Q+GM2V+q+wXnLKIA5sc k13jIb/rJch/otha5TYzgMzk2PHXxEGjeO8jl2UpbbCDl8U/j2lGnUKK1i5j5G8KoDSh u+qQ== X-Gm-Message-State: AOAM53033qZsmIYs1NdGdSVhFUv5qlE2lxPDTEGaR85OeW4uJqjjsVfY FL8u9kQ1kZLC42DDI75HOnOSRXsiI+zhlR376IyX/Q== X-Received: by 2002:a92:6511:: with SMTP id z17mr6428777ilb.232.1615648599075; Sat, 13 Mar 2021 07:16:39 -0800 (PST) MIME-Version: 1.0 References: <20210116170725.5245-1-dsmythies@telus.net> In-Reply-To: From: Doug Smythies Date: Sat, 13 Mar 2021 07:16:27 -0800 Message-ID: Subject: Re: [PATCH] tools/power/x86/turbostat: Fix TCC offset bit mask To: Len Brown Cc: Linux Kernel Mailing List , Linux PM list , dsmythies Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Mar 12, 2021 at 2:16 PM Len Brown wrote: > > Doug, > The offset works for control. > > However, it is erroneous to use it for reporting of the actual > temperature, like I did in turbostat. Agreed. I have been running with a correction for that for a while, and as discussed on Rui's thread. But this bit mask correction patch is still needed isn't it? for this: cpu4: MSR_IA32_TEMPERATURE_TARGET: 0x1a64100d (90 C) (100 default - 10 offset) which should be this: cpu4: MSR_IA32_TEMPERATURE_TARGET: 0x1a64100d (74 C) (100 default - 26 offset) But yes, I do now see the field size is only 4 bits for some parts. ... Doug > Thus, I'm going to revert the patch that added it's use in turbostat > for the Temperature column. > > thanks, > -Len > > On Fri, Mar 12, 2021 at 1:26 AM Doug Smythies wrote: > > > > Hi Len, > > > > > > thank you for your reply. > > > > On Thu, Mar 11, 2021 at 3:19 PM Len Brown wrote: > > > > > > Thanks for the close read, Doug. > > > > > > This field size actually varies from system to system, > > > but the reality is that the offset is never that big, and so the > > > smaller mask is sufficient. > > > > Disagree. > > > > I want to use an offset of 26. > > > > > Finally, this may all be moot, because there is discussion that using > > > the offset this way is simply erroneous. > > > > Disagree. > > It works great. > > As far as I know/recall I was the only person that responded to Rui's thread > > "thermal/intel: introduce tcc cooling driver" [1] > > And, I spent quite a bit of time doing so. > > However, I agree the response seems different between the two systems > > under test, Rui's and mine. > > > > [1] https://marc.info/?l=linux-pm&m=161070345329806&w=2 > > > > > stay tuned. > > > > O.K. > > > > ... Doug > > > > > > -Len > > > > > > > > > On Sat, Jan 16, 2021 at 12:07 PM Doug Smythies wrote: > > > > > > > > The TCC offset mask is incorrect, resulting in > > > > incorrect target temperature calculations, if > > > > the offset is big enough to exceed the mask size. > > > > > > > > Signed-off-by: Doug Smythies > > > > --- > > > > tools/power/x86/turbostat/turbostat.c | 2 +- > > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > > > diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c > > > > index 389ea5209a83..d7acdd4d16c4 100644 > > > > --- a/tools/power/x86/turbostat/turbostat.c > > > > +++ b/tools/power/x86/turbostat/turbostat.c > > > > @@ -4823,7 +4823,7 @@ int read_tcc_activation_temp() > > > > > > > > target_c = (msr >> 16) & 0xFF; > > > > > > > > - offset_c = (msr >> 24) & 0xF; > > > > + offset_c = (msr >> 24) & 0x3F; > > > > > > > > tcc = target_c - offset_c; > > > > > > > > -- > > > > 2.25.1 > > > > > > > > > > > > > -- > > > Len Brown, Intel Open Source Technology Center > > > > -- > Len Brown, Intel Open Source Technology Center