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Mon, 15 Mar 2021 05:50:52 +0000 From: Swapnil Kashinath Jakhade To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Philipp Zabel CC: "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , Lokesh Vutla Subject: RE: [PATCH v6 05/13] phy: cadence: cadence-sierra: Move all clk_get_*() to a separate function Thread-Topic: [PATCH v6 05/13] phy: cadence: cadence-sierra: Move all clk_get_*() to a separate function Thread-Index: AQHXFcSHaRA9XWOht0aMzEyF1fUB8KqAB6IA Date: Mon, 15 Mar 2021 05:50:52 +0000 Message-ID: References: <20210310154558.32078-1-kishon@ti.com> <20210310154558.32078-6-kishon@ti.com> In-Reply-To: <20210310154558.32078-6-kishon@ti.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-dg-ref: PG1ldGE+PGF0IG5tPSJib2R5LnR4dCIgcD0iYzpcdXNlcnNcc2pha2hhZGVcYXBwZGF0YVxyb2FtaW5nXDA5ZDg0OWI2LTMyZDMtNGE0MC04NWVlLTZiODRiYTI5ZTM1Ylxtc2dzXG1zZy02NTEzZTk2NS04NTUyLTExZWItODU0Ny1jOGY3NTA0NDIyZDhcYW1lLXRlc3RcNjUxM2U5NjYtODU1Mi0xMWViLTg1NDctYzhmNzUwNDQyMmQ4Ym9keS50eHQiIHN6PSIzODQ2IiB0PSIxMzI2MDI2MTA1MDQ4NjY5OTYiIGg9Ill3S3dmN3FRYXVqWHlla3dtUmQ4Y01xbmpSUT0iIGlkPSIiIGJsPSIwIiBibz0iMSIvPjwvbWV0YT4= x-dg-rorf: true authentication-results: ti.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: cadence.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN2PR07MB6160.namprd07.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 22b4adf9-cec4-4e75-6696-08d8e7764b61 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Mar 2021 05:50:52.8137 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: d36035c5-6ce6-4662-a3dc-e762e61ae4c9 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: EB3iGo5v674OlkSZQNat6cRA2ViMgfTVyvPS2MB8jFeykR9M+ftli3unKD/zZwF1XsRDzulGN9XsGMvJvNeMjLEoggs0yzP9o9SuPRK28jM= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLAPR07MB8258 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369,18.0.761 definitions=2021-03-15_01:2021-03-15,2021-03-15 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 adultscore=0 priorityscore=1501 bulkscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 spamscore=0 suspectscore=0 impostorscore=0 mlxscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2103150040 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Kishon Vijay Abraham I > Sent: Wednesday, March 10, 2021 9:16 PM > To: Kishon Vijay Abraham I ; Vinod Koul > ; Rob Herring ; Philipp Zabel > ; Swapnil Kashinath Jakhade > > Cc: linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Lokesh Vutl= a > > Subject: [PATCH v6 05/13] phy: cadence: cadence-sierra: Move all clk_get_= *() > to a separate function >=20 > EXTERNAL MAIL >=20 >=20 > No functional change. Group all devm_clk_get_optional() to a separate > function. >=20 > Signed-off-by: Kishon Vijay Abraham I > --- > drivers/phy/cadence/phy-cadence-sierra.c | 57 +++++++++++++++--------- > 1 file changed, 35 insertions(+), 22 deletions(-) >=20 Reviewed-by: Swapnil Jakhade Thanks & regards, Swapnil > diff --git a/drivers/phy/cadence/phy-cadence-sierra.c > b/drivers/phy/cadence/phy-cadence-sierra.c > index f7ba0ed416bc..7bf1b4c7774a 100644 > --- a/drivers/phy/cadence/phy-cadence-sierra.c > +++ b/drivers/phy/cadence/phy-cadence-sierra.c > @@ -477,6 +477,38 @@ static int cdns_regmap_init_blocks(struct > cdns_sierra_phy *sp, > return 0; > } >=20 > +static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, > + struct device *dev) > +{ > + struct clk *clk; > + int ret; > + > + clk =3D devm_clk_get_optional(dev, "phy_clk"); > + if (IS_ERR(clk)) { > + dev_err(dev, "failed to get clock phy_clk\n"); > + return PTR_ERR(clk); > + } > + sp->clk =3D clk; > + > + clk =3D devm_clk_get_optional(dev, "cmn_refclk_dig_div"); > + if (IS_ERR(clk)) { > + dev_err(dev, "cmn_refclk_dig_div clock not found\n"); > + ret =3D PTR_ERR(clk); > + return ret; > + } > + sp->cmn_refclk_dig_div =3D clk; > + > + clk =3D devm_clk_get_optional(dev, "cmn_refclk1_dig_div"); > + if (IS_ERR(clk)) { > + dev_err(dev, "cmn_refclk1_dig_div clock not found\n"); > + ret =3D PTR_ERR(clk); > + return ret; > + } > + sp->cmn_refclk1_dig_div =3D clk; > + > + return 0; > +} > + > static int cdns_sierra_phy_probe(struct platform_device *pdev) { > struct cdns_sierra_phy *sp; > @@ -487,7 +519,6 @@ static int cdns_sierra_phy_probe(struct > platform_device *pdev) > unsigned int id_value; > int i, ret, node =3D 0; > void __iomem *base; > - struct clk *clk; > struct device_node *dn =3D dev->of_node, *child; >=20 > if (of_get_child_count(dn) =3D=3D 0) > @@ -524,11 +555,9 @@ static int cdns_sierra_phy_probe(struct > platform_device *pdev) >=20 > platform_set_drvdata(pdev, sp); >=20 > - sp->clk =3D devm_clk_get_optional(dev, "phy_clk"); > - if (IS_ERR(sp->clk)) { > - dev_err(dev, "failed to get clock phy_clk\n"); > - return PTR_ERR(sp->clk); > - } > + ret =3D cdns_sierra_phy_get_clocks(sp, dev); > + if (ret) > + return ret; >=20 > sp->phy_rst =3D devm_reset_control_get(dev, "sierra_reset"); > if (IS_ERR(sp->phy_rst)) { > @@ -542,22 +571,6 @@ static int cdns_sierra_phy_probe(struct > platform_device *pdev) > return PTR_ERR(sp->apb_rst); > } >=20 > - clk =3D devm_clk_get_optional(dev, "cmn_refclk_dig_div"); > - if (IS_ERR(clk)) { > - dev_err(dev, "cmn_refclk_dig_div clock not found\n"); > - ret =3D PTR_ERR(clk); > - return ret; > - } > - sp->cmn_refclk_dig_div =3D clk; > - > - clk =3D devm_clk_get_optional(dev, "cmn_refclk1_dig_div"); > - if (IS_ERR(clk)) { > - dev_err(dev, "cmn_refclk1_dig_div clock not found\n"); > - ret =3D PTR_ERR(clk); > - return ret; > - } > - sp->cmn_refclk1_dig_div =3D clk; > - > ret =3D clk_prepare_enable(sp->clk); > if (ret) > return ret; > -- > 2.17.1