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[23.128.96.18]) by mx.google.com with ESMTP id h16si9996534ejt.695.2021.03.15.00.54.07; Mon, 15 Mar 2021 00:54:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230468AbhCOHwu (ORCPT + 99 others); Mon, 15 Mar 2021 03:52:50 -0400 Received: from inva021.nxp.com ([92.121.34.21]:49106 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230386AbhCOHwk (ORCPT ); Mon, 15 Mar 2021 03:52:40 -0400 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 6C7402030DF; Mon, 15 Mar 2021 08:52:39 +0100 (CET) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 83BAF2030D7; Mon, 15 Mar 2021 08:52:35 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 70A85402CB; Mon, 15 Mar 2021 08:52:30 +0100 (CET) From: Richard Zhu To: abel.vesa@nxp.com, shawnguo@kernel.org, ping.bai@nxp.com Cc: linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Richard Zhu Subject: [PATCH] clk: imx8mq: Correct the pcie1 sels Date: Mon, 15 Mar 2021 15:39:25 +0800 Message-Id: <1615793965-1422-2-git-send-email-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1615793965-1422-1-git-send-email-hongxing.zhu@nxp.com> References: <1615793965-1422-1-git-send-email-hongxing.zhu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org - The sys2_pll_50m should be one of the clock sels of PCIE_AUX clock, Change the sys2_pll_500m to sys2_pll_50m. - Correct one mis-spell of the imx8mq_pcie1_ctrl_sels definition, from "sys2_pll_250m" to "sys2_pll_333m". Signed-off-by: Richard Zhu --- drivers/clk/imx/clk-imx8mq.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index 4dd4ae9d022b..c66c196f396c 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -113,12 +113,12 @@ static const char * const imx8mq_disp_dtrc_sels[] = {"osc_25m", "vpu_pll_out", " static const char * const imx8mq_disp_dc8000_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll_out", "audio_pll2_out", }; static const char * const imx8mq_pcie1_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m", - "sys1_pll_800m", "sys2_pll_500m", "sys2_pll_250m", "sys3_pll_out", }; + "sys1_pll_800m", "sys2_pll_500m", "sys2_pll_333m", "sys3_pll_out", }; static const char * const imx8mq_pcie1_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4", }; -static const char * const imx8mq_pcie1_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_500m", "sys3_pll_out", +static const char * const imx8mq_pcie1_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_50m", "sys3_pll_out", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", }; static const char * const imx8mq_dc_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll_out", "clk_ext4", }; -- 2.17.1