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Mon, 15 Mar 2021 18:04:04 +0000 From: Krishna Reddy To: Eric Auger , "eric.auger.pro@gmail.com" , "iommu@lists.linux-foundation.org" , "linux-kernel@vger.kernel.org" , "kvm@vger.kernel.org" , "kvmarm@lists.cs.columbia.edu" , "will@kernel.org" , "joro@8bytes.org" , "maz@kernel.org" , "robin.murphy@arm.com" , "alex.williamson@redhat.com" CC: "jean-philippe@linaro.org" , "vivek.gautam@arm.com" , "zhangfei.gao@linaro.org" , Sachin Nikam , Yu-Huan Hsu , Bryan Huntsman , Vikram Sethi Subject: RE: [PATCH v13 00/15] SMMUv3 Nested Stage Setup (IOMMU part) Thread-Topic: [PATCH v13 00/15] SMMUv3 Nested Stage Setup (IOMMU part) Thread-Index: AQHWvZ0by+yuuitxUU+rB5qiY4c55qqGB4zA Date: Mon, 15 Mar 2021 18:04:04 +0000 Message-ID: References: <20201118112151.25412-1-eric.auger@redhat.com> In-Reply-To: <20201118112151.25412-1-eric.auger@redhat.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: redhat.com; dkim=none (message not signed) header.d=none;redhat.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BY5PR12MB3764.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3f220884-90d2-439b-494b-08d8e7dcb857 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Mar 2021 18:04:04.3994 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 9uwA0oGaTaKy5R93JBlOcS5uosMten7U3jfMfX1b+a9nN4eltmjGOfL4d02AEPFVU8HGvLvZkt/JOriBnUhsqg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Tested-by: Krishna Reddy > 1) pass the guest stage 1 configuration Validated Nested SMMUv3 translations for NVMe PCIe device from Guest VM alo= ng with patch series "v11 SMMUv3 Nested Stage Setup (VFIO part)" and QEMU p= atch series "vSMMUv3/pSMMUv3 2 stage VFIO integration" from v5.2.0-2stage-r= fcv8.=20 NVMe PCIe device is functional with 2-stage translations and no issues obse= rved. -KR