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Tue, 16 Mar 2021 19:15:50 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 16 Mar 2021 19:15:47 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 16 Mar 2021 19:15:47 +0800 From: Seiya Wang To: Rob Herring , Matthias Brugger CC: Jonathan Cameron , Lars-Peter Clausen , Peter Meerwald-Stadler , Ulf Hansson , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Greg Kroah-Hartman , Mark Brown , Daniel Lezcano , Thomas Gleixner , Wim Van Sebroeck , Guenter Roeck , Enric Balletbo i Serra , Hsin-Yi Wang , Seiya Wang , Fabien Parent , Sean Wang , Zhiyong Tao , Chaotian Jing , Wenbin Mei , Stanley Chu , Bayi Cheng , Chuanhong Guo , , , , , , , , , , Subject: [PATCH 10/10] arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile Date: Tue, 16 Mar 2021 19:14:43 +0800 Message-ID: <20210316111443.3332-11-seiya.wang@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210316111443.3332-1-seiya.wang@mediatek.com> References: <20210316111443.3332-1-seiya.wang@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-SNTS-SMTP: B9DB7DD2E633F284CF959A8FEAC37E05E53E7C6ABFFA4583C0A63A2D61DF0A162000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add basic chip support for Mediatek MT8195 Signed-off-by: Seiya Wang --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 29 ++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 477 ++++++++++++++++++++++++++++ 3 files changed, 507 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8195-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8195.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index deba27ab7657..aee4b9715d2f 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -16,4 +16,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts new file mode 100644 index 000000000000..82bb10e9a531 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Seiya Wang + */ +/dts-v1/; +#include "mt8195.dtsi" + +/ { + model = "MediaTek MT8195 evaluation board"; + compatible = "mediatek,mt8195-evb", "mediatek,mt8195"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi new file mode 100644 index 000000000000..356583fe4f03 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -0,0 +1,477 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Seiya Wang + */ + +/dts-v1/; + +#include +#include + +/ { + compatible = "mediatek,mt8195"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + clocks { + clk26m: oscillator0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + clk32k: oscillator1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "clk32k"; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55", "arm,armv8"; + reg = <0x000>; + enable-method = "psci"; + clock-frequency = <1701000000>; + capacity-dmips-mhz = <578>; + cpu-idle-states = <&cpuoff_l &clusteroff_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55", "arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + clock-frequency = <1701000000>; + capacity-dmips-mhz = <578>; + cpu-idle-states = <&cpuoff_l &clusteroff_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55", "arm,armv8"; + reg = <0x200>; + enable-method = "psci"; + clock-frequency = <1701000000>; + capacity-dmips-mhz = <578>; + cpu-idle-states = <&cpuoff_l &clusteroff_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55", "arm,armv8"; + reg = <0x300>; + enable-method = "psci"; + clock-frequency = <1701000000>; + capacity-dmips-mhz = <578>; + cpu-idle-states = <&cpuoff_l &clusteroff_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a78", "arm,armv8"; + reg = <0x400>; + enable-method = "psci"; + clock-frequency = <2171000000>; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&cpuoff_b &clusteroff_b>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a78", "arm,armv8"; + reg = <0x500>; + enable-method = "psci"; + clock-frequency = <2171000000>; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&cpuoff_b &clusteroff_b>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a78", "arm,armv8"; + reg = <0x600>; + enable-method = "psci"; + clock-frequency = <2171000000>; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&cpuoff_b &clusteroff_b>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a78", "arm,armv8"; + reg = <0x700>; + enable-method = "psci"; + clock-frequency = <2171000000>; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&cpuoff_b &clusteroff_b>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + idle-states { + entry-method = "arm,psci"; + cpuoff_l: cpuoff_l { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x00010001>; + local-timer-stop; + entry-latency-us = <50>; + exit-latency-us = <95>; + min-residency-us = <580>; + }; + cpuoff_b: cpuoff_b { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x00010001>; + local-timer-stop; + entry-latency-us = <45>; + exit-latency-us = <140>; + min-residency-us = <740>; + }; + clusteroff_l: clusteroff_l { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x01010002>; + local-timer-stop; + entry-latency-us = <55>; + exit-latency-us = <155>; + min-residency-us = <840>; + }; + clusteroff_b: clusteroff_b { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x01010002>; + local-timer-stop; + entry-latency-us = <50>; + exit-latency-us = <200>; + min-residency-us = <1000>; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + next-level-cache = <&l3_0>; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + next-level-cache = <&l3_0>; + }; + + l3_0: l3-cache { + compatible = "cache"; + }; + }; + + dsu-pmu { + compatible = "arm,dsu-pmu"; + interrupts = ; + cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, + <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + }; + + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupt-parent = <&gic>; + interrupts = ; + }; + + pmu-a78 { + compatible = "arm,cortex-a78-pmu"; + interrupt-parent = <&gic>; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer: timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + clock-frequency = <13000000>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + #redistributor-regions = <1>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, + <0 0x0c040000 0 0x200000>; + interrupts = ; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; + }; + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; + }; + }; + }; + + watchdog: watchdog@10007000 { + compatible = "mediatek,mt8195-wdt", "mediatek,mt6589-wdt"; + reg = <0 0x10007000 0 0x100>; + }; + + systimer: timer@10017000 { + compatible = "mediatek,mt8195-timer", "mediatek,mt6765-timer"; + reg = <0 0x10017000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>; + }; + + uart0: serial@11001100 { + compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart"; + reg = <0 0x11001100 0 0x100>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11001200 { + compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart"; + reg = <0 0x11001200 0 0x100>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "baud", "bus"; + }; + + uart2: serial@11001300 { + compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart"; + reg = <0 0x11001300 0 0x100>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart3: serial@11001400 { + compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart"; + reg = <0 0x11001400 0 0x100>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart4: serial@11001500 { + compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart"; + reg = <0 0x11001500 0 0x100>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart5: serial@11001600 { + compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart"; + reg = <0 0x11001600 0 0x100>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + auxadc: auxadc@11002000 { + compatible = "mediatek,mt8195-auxadc", "mediatek,mt8173-auxadc"; + reg = <0 0x11002000 0 0x1000>; + clocks = <&clk26m>; + clock-names = "main"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc"; + reg = <0 0x11230000 0 0x10000>, + <0 0x11f50000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>, <&clk26m>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc"; + reg = <0 0x11240000 0 0x1000>, + <0 0x11c70000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>, <&clk26m>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + nor_flash: nor@1132c000 { + compatible = "mediatek,mt8195-nor", "mediatek,mt8173-nor"; + reg = <0 0x1132c000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "spi", "sf"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + u3phy2: usb-phy2@11c40000 { + compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2"; + clocks = <&clk26m>; + clock-names = "u3phya_ref"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11c40000 0x700>; + status = "disabled"; + + u2port2: usb2-phy2@0 { + reg = <0x0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "disabled"; + }; + }; + + u3phy3: usb-phy3@11c50000 { + compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2"; + clocks = <&clk26m>; + clock-names = "u3phya_ref"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11c50000 0x700>; + status = "disabled"; + + u2port3: usb2-phy3@0 { + reg = <0x0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "disabled"; + }; + }; + + u3phy1: usb-phy1@11e30000 { + compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2"; + clocks = <&clk26m>; + clock-names = "u3phya_ref"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11e30000 0xe00>; + status = "disabled"; + + u2port1: usb2-phy1@0 { + reg = <0x0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "disabled"; + }; + + u3port1: usb3-phy1@700 { + reg = <0x700 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "disabled"; + }; + }; + + u3phy0: usb-phy0@11e40000 { + compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2"; + clocks = <&clk26m>; + clock-names = "u3phya_ref"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11e40000 0xe00>; + status = "disabled"; + + u2port0: usb2-phy0@0 { + reg = <0x0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "disabled"; + }; + + u3port0: usb3-phy0@700 { + reg = <0x700 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "disabled"; + }; + }; + + ufsphy: phy@11fa0000 { + compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; + reg = <0 0x11fa0000 0 0xc000>; + clocks = <&clk26m>, <&clk26m>; + clock-names = "unipro", "mp"; + #phy-cells = <0>; + }; + }; +}; -- 2.14.1