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[35.233.69.230]) by smtp.gmail.com with ESMTPSA id b186sm3074930wmc.44.2021.03.16.05.53.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Mar 2021 05:53:55 -0700 (PDT) Date: Tue, 16 Mar 2021 12:53:53 +0000 From: Quentin Perret To: Mate Toth-Pal Cc: catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com, android-kvm@google.com, seanjc@google.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, kernel-team@android.com, kvmarm@lists.cs.columbia.edu, tabba@google.com, ardb@kernel.org, mark.rutland@arm.com, dbrazdil@google.com Subject: Re: [PATCH v5 33/36] KVM: arm64: Wrap the host with a stage 2 Message-ID: References: <20210315143536.214621-1-qperret@google.com> <20210315143536.214621-34-qperret@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tuesday 16 Mar 2021 at 13:28:42 (+0100), Mate Toth-Pal wrote: > Testing the latest version of the patchset, we seem to have found another > thing related to FEAT_S2FWB. Argh! I wish I could put my hands on hardware with FWB. Thanks again for the report. > This function always sets Normal memory in the stage 2 table, even if the > address in stage 1 was mapped as a device memory. However with the current > settings for normal memory (i.e. MT_S2_FWB_NORMAL being defined to 6) > according to the architecture (See Arm ARM, 'D5.5.5 Stage 2 memory region > type and cacheability attributes when FEAT_S2FWB is implemented') the > resulting attributes will be 'Normal Write-Back' even if the stage 1 mapping > sets device memory. Accessing device memory mapped like this causes an > SError on some platforms with FEAT_S2FWB being implemented. Right. > Changing the value of MT_S2_FWB_NORMAL to 7 would change this behavior, and > the resulting memory type would be device. Sounds like the correct fix here -- see below. > Another solution would be to add an else branch to the last 'if' above like > this: > > diff --git a/arch/arm64/kvm/hyp/nvhe/mem_protect.c > b/arch/arm64/kvm/hyp/nvhe/mem_protect.c > index fffa432ce3eb..54e5d3b0b2e1 100644 > --- a/arch/arm64/kvm/hyp/nvhe/mem_protect.c > +++ b/arch/arm64/kvm/hyp/nvhe/mem_protect.c > @@ -214,6 +214,8 @@ static int host_stage2_idmap(u64 addr) > >         if (is_memory) >                 prot |= KVM_PGTABLE_PROT_X; > +       else > +               prot |= KVM_PGTABLE_PROT_DEVICE; > >         hyp_spin_lock(&host_kvm.lock); >         ret = kvm_pgtable_stage2_find_range(&host_kvm.pgt, addr, prot, > &range); While this would work in this particular case, I don't think we should force all non-RAM accesses as device as the host may have reasons not to want this (e.g. accessing SRAM). Your first suggestions allows us to do just that, so it is preferable I think. Thanks, Quentin