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Date:   Tue, 16 Mar 2021 20:50:14 +0200
From:   Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
To:     Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc:     Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
        Andreas =?iso-8859-1?Q?F=E4rber?= <afaerber@suse.de>,
        Michael Turquette <mturquette@baylibre.com>,
        Edgar Bernardi Righi <edgar.righi@lsitec.org.br>,
        linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org
Subject: Re: [PATCH 4/6] clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl
 S500 SoC
Message-ID: <20210316185014.GD1111731@BV030612LT>
References: <cover.1615221459.git.cristian.ciocaltea@gmail.com>
 <58225ced4893018792d581c0476a0f1c70e08907.1615221459.git.cristian.ciocaltea@gmail.com>
 <20210316054547.GD1798@thinkpad>
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In-Reply-To: <20210316054547.GD1798@thinkpad>
Precedence: bulk

On Tue, Mar 16, 2021 at 11:15:47AM +0530, Manivannan Sadhasivam wrote:
> On Mon, Mar 08, 2021 at 07:18:29PM +0200, Cristian Ciocaltea wrote:
> > There are a few issues with the setup of the Actions Semi Owl S500 SoC's
> > clock chain involving AHPPREDIV, H and AHB clocks:
> > 
> > * AHBPREDIV clock is defined as a muxer only, although it also acts as
> >   a divider.
> > * H clock is defined as a standard divider, although the raw value zero
> >   is not supported.
> 
> What do you mean by not supported? The datasheet lists "0" as the valid divisor
> value for divide by 1.

Unfortunately CMU_BUSCLK1 is not documented in my S500 Datasheet
(Version: 1.6, 2016-03-07). Do you have a newer (or a more official)
one?

The reference xapp-le code snipped is:

static struct owl_div divider_H_CLK = {
    .type = DIV_T_NATURE,
    .range_from = 1,  /* reserve H_CLK divsor 1 */
    .range_to = 3,
    .reg = &divbit_H_CLK,
};

Not sure why divisor 1 has been reserved..

Thanks,
Cristi

> Rest looks good to me.
> 
> Thanks,
> Mani
> 
[...]