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From:   Anup Patel <anup@brainfault.org>
Date:   Wed, 17 Mar 2021 14:00:35 +0530
Message-ID: <CAAhSdy1wzH4N-4kFS63sOWSNdX7w9i8ZS9od6hfruMTMEOY=_g@mail.gmail.com>
Subject: Re: [PATCH] riscv,entry: fix misaligned base for excp_vect_table
To:     Zihao Yu <yuzihao@ict.ac.cn>
Cc:     Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        linux-riscv <linux-riscv@lists.infradead.org>,
        "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>
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On Wed, Mar 17, 2021 at 1:48 PM Zihao Yu <yuzihao@ict.ac.cn> wrote:
>
> * In RV64, the size of each entry in excp_vect_table is 8 bytes. If the
>   base of the table is not 8-byte aligned, loading an entry in the table
>   will raise a misaligned exception. Although such exception will be
>   handled by opensbi/bbl, this still causes performance degradation.
>
> Signed-off-by: Zihao Yu <yuzihao@ict.ac.cn>

Looks good to me.

Reviewed-by: Anup Patel <anup@brainfault.org>

Regards,
Anup

> ---
>  arch/riscv/kernel/entry.S | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
> index 744f3209c..76274a4a1 100644
> --- a/arch/riscv/kernel/entry.S
> +++ b/arch/riscv/kernel/entry.S
> @@ -447,6 +447,7 @@ ENDPROC(__switch_to)
>  #endif
>
>         .section ".rodata"
> +       .align LGREG
>         /* Exception vector table */
>  ENTRY(excp_vect_table)
>         RISCV_PTR do_trap_insn_misaligned
> --
> 2.20.1
>
>
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