Received: by 2002:a05:6a10:9848:0:0:0:0 with SMTP id x8csp34481pxf; Wed, 17 Mar 2021 14:35:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzpRuPmPRXsuDQy7If7i5RmkhwCIohRISfQfutfiDcdeUsPsr6NwZDGmdXzFGSqdcELQtyH X-Received: by 2002:a17:907:20f5:: with SMTP id rh21mr37641179ejb.27.1616016918575; Wed, 17 Mar 2021 14:35:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616016918; cv=none; d=google.com; s=arc-20160816; b=sjRBqmG3aGi5AkRPvkyVx2TKeoX6v+h333FgP2ho+MUz2WzXf+uovU7YEXJ8Y+6sDz Rr8hd0kZHg8aQx3cS25ipgU3IGhqcmCaY5fiASJ/1n4oQiLN0UPo81O1aoak4HTG+ZSV 4RczaM9B3POlD87gWOU6mihUtsQzjHoSQ0khIQPC86uF0DUtyjb68Kge3gbrUmMeajUO NFZU6/5DKK6GXvFHf8a9gq8RzVvjt+vee5n0ywXS3Ssz7Ha1qAhmwhHJoL2u651QH8QN bgHTtG4Pvxhd8QduiV7RvnDhlu+4nEEluL0jOl8D+1rbUcWekpHwS0FyWYjxoak46wdI xk7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-transfer-encoding :content-disposition:mime-version:references:message-id:subject:cc :to:from:date; bh=AKAtkr89dUWh489hHbPAdXBixphRlAWMJKtGyUjcZCY=; b=XVketqvIOn3irmgADCSCUcRgPt2IoR44qyvep0EhE7BCgnUdFbP5ZFT8ekEMKFH5sK q2O3e7bE2dRt/Jc5mNi5wv/2Zva0H2xt1gRJQNn9phAe9VFIV47RbuX5y6nblFJqBWJH AShmqx+CpvXF8//D61ixTDWo6QAqyLT8kW9RslLBXkRCrB/jjzbm/TEncwXm7YCViaz/ l37AalSqUeXUPKo9O5SMW4h9N+J5agEHl2XydWnYTCpHDVhBHVtEUuV/3R5LVCkARVaM pg4opiY10Eie1ADXfMgSIp20JeexbzTu3qd9GiA7pow0XOlTf4TKjRCRnd0/ABOCXQXK wMHQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id y16si12026612edd.467.2021.03.17.14.34.56; Wed, 17 Mar 2021 14:35:18 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232561AbhCQRuC (ORCPT + 99 others); Wed, 17 Mar 2021 13:50:02 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:33222 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232483AbhCQRtk (ORCPT ); Wed, 17 Mar 2021 13:49:40 -0400 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1lMaIR-00BV78-QU; Wed, 17 Mar 2021 18:49:27 +0100 Date: Wed, 17 Mar 2021 18:49:27 +0100 From: Andrew Lunn To: =?iso-8859-1?Q?=C1lvaro_Fern=E1ndez?= Rojas Cc: Jonas Gorski , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/2] net: mdio: Add BCM6368 MDIO mux bus controller Message-ID: References: <20210308184102.3921-1-noltari@gmail.com> <20210308184102.3921-3-noltari@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > BCM6368 (and newer) SoCs have an integrated ethernet switch controller with dedicated internal phys, but it also supports connecting to external phys not integrated in the internal switch. > Ports 0-3 are internal, ports 4-7 are external and can be connected to external switches or phys and port 8 is the CPU. > This MDIO bus device is integrated in the BCM63xx switch registers, which corresponds to the same registers present in drivers/net/dsa/b53/b53_regs.h. > As you can see in the source code, registers are the same for the internal and external bus. The only difference is that if MDIOC_EXT_MASK (bit 16) is set, the MDIO bus accessed will be the external, and on the contrary, if bit 16 isn’t set, the MDIO bus accessed will be the internal one. > > I don’t know if this answers your question, but I think that adding it as mdiomux is the way to go. Hi Álvaro The Marvell mv88e6390 family of switches has a very similar setup. An internal and an external MDIO bus, one bit difference in a register. When i wrote the code for that, i decided it was not a mux as such, but two MDIO busses. So i register two MDIO busses, and rely on a higher level switch register mutex to prevent parallel operations on the two busses. The reason i decided it was not a mux, is that all the other mux drivers are separate drivers which rely on another MDIO bus driver. The mux driver gets a handle to the underlying MDIO bus driver, and and builds on it. Here you have it all combined in one, so it does not follow the pattern. So if you want to use a max, please break this up into an MDIO driver, and a mux driver. Or have one driver which registers two mdio busses, no mux. Andrew