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Wed, 17 Mar 2021 22:29:35 +0000 Received: from [172.17.173.69] (172.20.145.6) by mail.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2 via Frontend Transport; Wed, 17 Mar 2021 22:29:34 +0000 X-Nvconfidentiality: public To: , , , , , CC: From: Dipen Patel Subject: GTE - The hardware timestamping engine Message-ID: <4c46726d-fa35-1a95-4295-bca37c8b6fe3@nvidia.com> Date: Wed, 17 Mar 2021 15:33:51 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 18812a2e-be0a-4d0b-0a19-08d8e994251b X-MS-TrafficTypeDiagnostic: BL1PR12MB5269: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: pOFYI86gjEI4x/Ri/X9nThrp1Vieh6UDCLampAG7n2LFYIcu4dSzDNbyAdhjBS9PoFmr4y8+RUzpTnBhpyeakjrZQ/JyraKUQ+WMn4jB25XSzpqdpSODcknGwW7vBTS1oIHUd/IowSrrDyqtHEnZGgFmkphrwSyxQCe9k09uzWtIm1UGk2/B9HGzj8yZmA8+7WTkHdSjijVqaxFWrrVIHfJlDsjt0HVWEm6j0mPqHU59MFwmd3doqwSgCwgA/Mt7kGBvOWDn/tkT7sGoq2+2E+tdN2cu/YrLHUQNjJOD5P6en42+1WPoP9rSRXiwROH4UIBz2QtpIzbZyLFFkO03kwu4eZdzxuVGO0Lb9iq3MVxUnJq8Mzrl/M4di4am6+l8gg5R2uTinFVWGozIzFrJuieciYID0mB6z8BPpjIt8mIjIKqxucHX0gFfN6GRgtxQE+qniSxFUTIpJRKCIk9MYQNQNmaT0JkPl41bv6QwWGCy7GAVOu/NnBddoEEvzjfnKO+n+ckgFZoipx7HFYaul83G9PpFMPeNwklcrgzZ7+YfiGzoNXLqm040RO2sClzbi/99efdRzOS3t3SE72hgAmNDV5VNeJ7+hNRX0Fsi3VCCyn6DK3rWntNjamOnvUT3A8g7mlfkirpwzi0Em6OsN/ECqHsiWZBm1cz/e7ZnMhRvamXG1d8oGiwLOHaHWaV3gzruPpkYyttqwN/nW7ZuTR8lvbAyoe/e/sE6T7mW7ZY= X-Forefront-Antispam-Report: CIP:216.228.112.35;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:schybrid04.nvidia.com;CAT:NONE;SFS:(4636009)(376002)(346002)(136003)(396003)(39860400002)(46966006)(36840700001)(336012)(82310400003)(2616005)(4326008)(36756003)(316002)(34020700004)(36860700001)(426003)(8676002)(83380400001)(36906005)(8936002)(86362001)(47076005)(82740400003)(70206006)(5660300002)(478600001)(26005)(186003)(7636003)(70586007)(110136005)(2906002)(16576012)(6666004)(31696002)(31686004)(356005)(43740500002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2021 22:29:35.8836 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 18812a2e-be0a-4d0b-0a19-08d8e994251b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.35];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT039.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5269 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi All, I wanted to discuss few implementation details regarding the GTE module and wanted to know your feedback on certain aspects as below. ================== GTE introductions: ================== Nvidia Tegra SoCs have generic timestamping engine (GTE) hardware module which can monitor SoC signals like IRQ lines and GPIO lines for state change, upon detecting the change, it can timestamp and store in its internal hardware FIFO. The advantage of the GTE module can be realized in applications like robotics or autonomous vehicle where it can help record events with precise timestamp. The GTE module however complicates the thing for GPIO monitoring compare to IRQ lines as it has dependency on GPIO controller and that is where I will probably will need your feedback to figure few things out before sending the patches for the review. The below is the rough sequence to enable the hw timestamp for a given signal using GTE module to put things into perspective. ============ For GPIO: ============ 1. GPIO has to be configured as input and IRQ must be enabled. 2. Ask GPIO controller driver to set corresponding timestamp bit in the specified GPIO config register. 3. Translate GPIO specified by the client to its internal bitmap. 3.a For example, If client specifies GPIO line 31, it could be bit 13 of GTE register. 4. Set internal bits to enable monitoring in GTE module 5. Additionally GTE driver can open up lanes for the user space application as a client and can send timestamping events directly to the application. ============ For IRQ: ============ x. Client sends IRQ line number to GTE driver y. There is no need to translate as there is one to one correspondence with its internal bitmap, for example, IRQ line 31 will be bit 31 of the GTE internal register. z. Set the required bits. ==================================================================== Doubts (specifically for the bullet 1,2,3 from GPIO section above): ==================================================================== b. Should GTE driver expect its client to send GPIO number as per the GPIO controller/framework numbering/namespace scheme? b.1 The possible issues with this approach are: b.1.1 It hast to make of_find_gpiochip_by_node function public which GTE driver can use to confirm GPIO number that client sent is indeed belongs to the controller which supports the timestamp functions as not all the GPIO controllers support it. b.1.2 GTE driver will need GPIO controller node either passed through its own device tree or through some other methods (if at all exist) to facilitate b.1.1 c. How GTE driver can talk to GPIO framework regarding bullet 2? c.1 If it is through some callbacks then have to add "timestamp_control" like function hook in the gpio framework structure. This is under assumption bullet b is GPIO numbering scheme, we can then pass the same GPIO number to this hook to enable timestamp bit in GPIO controller. d GPIO logical numbering happens at the run time so GTE driver has to take care b.1.1, b.1.2 and c.1. e. Using above b.1.1, b.1.2 and c.1, GTE module can do bullet 1 and 2 for its clients or at least bullet 2. f. The other alternative is to have GTE its own GPIO numbering for its clients. f.1 This approach completely decouples GPIO controller and GTE, where client will be responsible for bullet 1 and gpio controller driver will be responsible for the bullet 2 and possibly set timestamp bit of all the GPIOs it supports during probe as real timestamping starts anyway after GTE driver programs its corresponding registers so can be considered harmless. f.2. I am more leaning towards this approach. =============================================== Doubts regarding the place it in the kernel: =============================================== g. Does GTE deserve its own subsystem or should it be consumed as part of some other subsystems? g.1 GTE GPIO timestamp monitoring comes very close to what we already have in the gpiolib, more specifically lineevent part. Having said that however if I were to add GTE inside GPIO framework "somehow", it will require non-trivial gpio framework changes and at the same time it will make GTE module fragmented since GTE also timestamps other signals besides GPIO like IRQ as mentioned previously. h. I am more leaning towards having its own subsystem. Best Regards, Dipen Patel