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From:   Nadav Amit <nadav.amit@gmail.com>
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Subject: =?utf-8?Q?Re=3A_A_problem_of_Intel_IOMMU_hardware_=EF=BC=9F?=
Date:   Thu, 18 Mar 2021 00:48:37 -0700
In-Reply-To: <a0ca6dd974be42878a8f51b0a7bbe00f@huawei.com>
Cc:     Lu Baolu <baolu.lu@linux.intel.com>,
        Alex Williamson <alex.williamson@redhat.com>,
        "dwmw2@infradead.org" <dwmw2@infradead.org>,
        "joro@8bytes.org" <joro@8bytes.org>,
        "will@kernel.org" <will@kernel.org>,
        "iommu@lists.linux-foundation.org" <iommu@lists.linux-foundation.org>,
        LKML <linux-kernel@vger.kernel.org>,
        "Gonglei (Arei)" <arei.gonglei@huawei.com>,
        chenjiashang <chenjiashang@huawei.com>,
        "Subo (Subo, Cloud Infrastructure Service Product Dept.)" 
        <subo7@huawei.com>
To:     "Longpeng (Mike, Cloud Infrastructure Service Product Dept.)" 
        <longpeng2@huawei.com>
References: <670baaf8-4ff8-4e84-4be3-030b95ab5a5e@huawei.com>
 <692186fd-42b8-4054-ead2-f6c6b1bf5b2d@linux.intel.com>
 <20210317091820.5f4ab69e@omen.home.shazbot.org>
 <87a5f90a-d1ea-fe7a-2577-fdfdf25f8fd7@linux.intel.com>
 <a0ca6dd974be42878a8f51b0a7bbe00f@huawei.com>
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> On Mar 17, 2021, at 9:46 PM, Longpeng (Mike, Cloud Infrastructure =
Service Product Dept.) <longpeng2@huawei.com> wrote:
>=20

[Snip]

>=20
> NOTE, the magical thing happen...(*Operation-4*) we write the PTE
> of Operation-1 from 0 to 0x3 which means can Read/Write, and then
> we trigger DMA read again, it success and return the data of HPA 0 !!
>=20
> Why we modify the older page table would make sense ? As we
> have discussed previously, the cache flush part of the driver is =
correct,
> it call flush_iotlb after (b) and no need to flush after (c). But the =
result
> of the experiment shows the older page table or older caches is =
effective
> actually.
>=20
> Any ideas ?

Interesting. Sounds as if there is some page-walk cache that was not
invalidated properly.


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