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From:   Anup Patel <anup@brainfault.org>
Date:   Thu, 18 Mar 2021 16:32:18 +0530
Message-ID: <CAAhSdy0ex1PjGa+=KgkSYFd+BteH7txJSrRdOhZnetwXaL42hQ@mail.gmail.com>
Subject: Re: [RFC PATCH 7/8] dt-bindings: Add bindings documentation for
 RISC-V idle states
To:     Rob Herring <robh@kernel.org>
Cc:     Anup Patel <anup.patel@wdc.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Palmer Dabbelt <palmerdabbelt@google.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Ulf Hansson <ulf.hansson@linaro.org>,
        "Rafael J . Wysocki" <rjw@rjwysocki.net>,
        Pavel Machek <pavel@ucw.cz>,
        Sandeep Tripathy <milun.tripathy@gmail.com>,
        Atish Patra <atish.patra@wdc.com>,
        Alistair Francis <Alistair.Francis@wdc.com>,
        Liush <liush@allwinnertech.com>, devicetree@vger.kernel.org,
        linux-riscv <linux-riscv@lists.infradead.org>,
        "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>,
        "open list:THERMAL" <linux-pm@vger.kernel.org>,
        linux-arm-kernel <linux-arm-kernel@lists.infradead.org>
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On Tue, Mar 16, 2021 at 9:24 PM Rob Herring <robh@kernel.org> wrote:
>
> On Sun, Mar 7, 2021 at 8:18 PM Anup Patel <anup@brainfault.org> wrote:
> >
> > On Sat, Mar 6, 2021 at 4:52 AM Rob Herring <robh@kernel.org> wrote:
> > >
> > > On Sun, Feb 21, 2021 at 03:07:57PM +0530, Anup Patel wrote:
> > > > The RISC-V CPU idle states will be described in DT under the
> > > > /cpus/riscv-idle-states DT node. This patch adds the bindings
> > > > documentation for riscv-idle-states DT nodes and idle state DT
> > > > nodes under it.
> > > >
> > > > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > > > ---
> > > >  .../bindings/riscv/idle-states.yaml           | 250 ++++++++++++++++++
> > > >  1 file changed, 250 insertions(+)
> > > >  create mode 100644 Documentation/devicetree/bindings/riscv/idle-states.yaml
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/riscv/idle-states.yaml b/Documentation/devicetree/bindings/riscv/idle-states.yaml
> > > > new file mode 100644
> > > > index 000000000000..3eff763fed23
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/riscv/idle-states.yaml
> > > > @@ -0,0 +1,250 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > +%YAML 1.2
> > > > +---
> > > > +$id: http://devicetree.org/schemas/riscv/idle-states.yaml#
> > > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > +
> > > > +title: RISC-V idle states binding description
> > > > +
> > > > +maintainers:
> > > > +  - Anup Patel <anup.patel@wdc.com>
> > > > +
> > > > +description: |+
> > > > +  RISC-V systems can manage power consumption dynamically, where HARTs
> > > > +  (or CPUs) [1] can be put in different platform specific suspend (or
> > > > +  idle) states (ranging from simple WFI, power gating, etc). The RISC-V
> > > > +  SBI [2] hart state management extension provides a standard mechanism
> > > > +  for OSes to request HART state transitions.
> > > > +
> > > > +  The platform specific suspend (or idle) states of a hart can be either
> > > > +  retentive or non-rententive in nature. A retentive suspend state will
> > > > +  preserve hart register and CSR values for all privilege modes whereas
> > > > +  a non-retentive suspend state will not preserve hart register and CSR
> > > > +  values. The suspend (or idle) state entered by executing the WFI
> > > > +  instruction is considered standard on all RISC-V systems and therefore
> > > > +  must not be listed in device tree.
> > > > +
> > > > +  The device tree binding definition for RISC-V idle states described
> > > > +  in this document is quite similar to the ARM idle states [3].
> > > > +
> > > > +  References
> > > > +
> > > > +  [1] RISC-V Linux Kernel documentation - CPUs bindings
> > > > +      Documentation/devicetree/bindings/riscv/cpus.yaml
> > > > +
> > > > +  [2] RISC-V Supervisor Binary Interface (SBI)
> > > > +      http://github.com/riscv/riscv-sbi-doc/riscv-sbi.adoc
> > > > +
> > > > +  [3] ARM idle states binding description - Idle states bindings
> > > > +      Documentation/devicetree/bindings/arm/idle-states.yaml
> > >
> > > I'd assume there's common parts we can share.
> >
> > Yes, except few properties most are the same.
> >
> > We can have a shared DT bindings for both ARM and RISC-V but
> > both architectures will always have some architecture specific details
> > (or properties) which need to be documented under arch specific
> > DT documentation. Is it okay if this is done as a separate series ?
>
> No...

Okay, I will create a common DT bindings for both ARM and RISC-V
in the next revision.

>
> > > > +
> > > > +properties:
> > > > +  $nodename:
> > > > +    const: riscv-idle-states
> > >
> > > Just 'idle-states' like Arm.
> >
> > I had tried "idle-states" node name but DT bindings check complaints
> > conflict with ARM idle state bindings.
>
> ...and this being one reason why.
>
> Actually, I think this can all be in 1 doc if you want. It's fine with
> me if a common doc has RiscV and Arm specific properties.

Sure, will add common DT bindings.

>
> > > > +
> > > > +patternProperties:
> > > > +  "^(cpu|cluster)-":
> > > > +    type: object
> > > > +    description: |
> > > > +      Each state node represents an idle state description and must be
> > > > +      defined as follows.
> > > > +
> > >
> > >        additionalProperties: false
> >
> > okay, will update.
> >
> > >
> > > > +    properties:
> > > > +      compatible:
> > > > +        const: riscv,idle-state
> > > > +
> > > > +      local-timer-stop:
> > > > +        description:
> > > > +          If present the CPU local timer control logic is lost on state
> > > > +          entry, otherwise it is retained.
> > > > +        type: boolean
> > > > +
> > > > +      entry-latency-us:
> > > > +        description:
> > > > +          Worst case latency in microseconds required to enter the idle state.
> > > > +
> > > > +      exit-latency-us:
> > > > +        description:
> > > > +          Worst case latency in microseconds required to exit the idle state.
> > > > +          The exit-latency-us duration may be guaranteed only after
> > > > +          entry-latency-us has passed.
> > > > +
> > > > +      min-residency-us:
> > > > +        description:
> > > > +          Minimum residency duration in microseconds, inclusive of preparation
> > > > +          and entry, for this idle state to be considered worthwhile energy
> > > > +          wise (refer to section 2 of this document for a complete description).
> > > > +
> > > > +      wakeup-latency-us:
> > > > +        description: |
> > > > +          Maximum delay between the signaling of a wake-up event and the CPU
> > > > +          being able to execute normal code again. If omitted, this is assumed
> > > > +          to be equal to:
> > > > +
> > > > +            entry-latency-us + exit-latency-us
> > > > +
> > > > +          It is important to supply this value on systems where the duration
> > > > +          of PREP phase (see diagram 1, section 2) is non-neglibigle. In such
> > > > +          systems entry-latency-us + exit-latency-us will exceed
> > > > +          wakeup-latency-us by this duration.
> > > > +
> > > > +      idle-state-name:
> > > > +        $ref: /schemas/types.yaml#/definitions/string
> > > > +        description:
> > > > +          A string used as a descriptive name for the idle state.
> > > > +
> > > > +    required:
> > > > +      - compatible
> > > > +      - entry-latency-us
> > > > +      - exit-latency-us
> > > > +      - min-residency-us
> > > > +
> > > > +additionalProperties: false
> >
> > I will move this up.
>
> TBC, you need this at 2 levels. Both the idle-states node and child nodes.

Sure, I will add at both levels.

Regards,
Anup